Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31516 )
Change subject: dev-arm: Implement LevelSensitive PPIs in GICv3
......................................................................
dev-arm: Implement LevelSensitive PPIs in GICv3
Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31516
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
3 files changed, 53 insertions(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 8e75b1c..83f2c83 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -193,8 +193,12 @@
}
void
-Gicv3::clearPPInt(uint32_t num, uint32_t cpu)
+Gicv3::clearPPInt(uint32_t int_id, uint32_t cpu)
{
+ panic_if(cpu >= redistributors.size(), "Invalid cpuID clearing PPI!");
+ DPRINTF(Interrupt, "Gicv3::clearPPInt(): received PPI %d
cpuTarget %#x\n",
+ int_id, cpu);
+ redistributors[cpu]->clearPPInt(int_id);
}
void
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index 5fceed5..3390393 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@
irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
+ irqPendingIspendr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX,
Gicv3::INT_EDGE_TRIGGERED),
@@ -509,6 +510,7 @@
"(GICR_ISPENDR0): int_id %d (PPI) "
"pending bit set\n", int_id);
irqPending[int_id] = true;
+ irqPendingIspendr[int_id] = true;
}
}
@@ -526,7 +528,7 @@
bool clear = data & (1 << int_id) ? 1 : 0;
- if (clear) {
+ if (clear && treatAsEdgeTriggered(int_id)) {
irqPending[int_id] = false;
}
}
@@ -710,12 +712,24 @@
assert((int_id >= Gicv3::SGI_MAX) &&
(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
irqPending[int_id] = true;
+ irqPendingIspendr[int_id] = false;
DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): "
"int_id %d (PPI) pending bit set\n", int_id);
updateDistributor();
}
void
+Gicv3Redistributor::clearPPInt(uint32_t int_id)
+{
+ assert((int_id >= Gicv3::SGI_MAX) &&
+ (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
+
+ if (isLevelSensitive(int_id)) {
+ irqPending[int_id] = false;
+ }
+}
+
+void
Gicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
{
assert(int_id < Gicv3::SGI_MAX);
@@ -747,6 +761,7 @@
if (!forward) return;
irqPending[int_id] = true;
+ irqPendingIspendr[int_id] = false;
DPRINTF(GIC, "Gicv3ReDistributor::sendSGI(): "
"int_id %d (SGI) pending bit set\n", int_id);
updateDistributor();
@@ -977,7 +992,9 @@
void
Gicv3Redistributor::activateIRQ(uint32_t int_id)
{
- irqPending[int_id] = false;
+ if (treatAsEdgeTriggered(int_id)) {
+ irqPending[int_id] = false;
+ }
irqActive[int_id] = true;
}
@@ -1037,6 +1054,7 @@
SERIALIZE_CONTAINER(irqGroup);
SERIALIZE_CONTAINER(irqEnabled);
SERIALIZE_CONTAINER(irqPending);
+ SERIALIZE_CONTAINER(irqPendingIspendr);
SERIALIZE_CONTAINER(irqActive);
SERIALIZE_CONTAINER(irqPriority);
SERIALIZE_CONTAINER(irqConfig);
@@ -1058,6 +1076,7 @@
UNSERIALIZE_CONTAINER(irqGroup);
UNSERIALIZE_CONTAINER(irqEnabled);
UNSERIALIZE_CONTAINER(irqPending);
+ UNSERIALIZE_CONTAINER(irqPendingIspendr);
UNSERIALIZE_CONTAINER(irqActive);
UNSERIALIZE_CONTAINER(irqPriority);
UNSERIALIZE_CONTAINER(irqConfig);
diff --git a/src/dev/arm/gic_v3_redistributor.hh
b/src/dev/arm/gic_v3_redistributor.hh
index ee92bc7..7def1a2 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -153,6 +153,7 @@
std::vector <uint8_t> irqGroup;
std::vector <bool> irqEnabled;
std::vector <bool> irqPending;
+ std::vector <bool> irqPendingIspendr;
std::vector <bool> irqActive;
std::vector <uint8_t> irqPriority;
std::vector <Gicv3::IntTriggerType> irqConfig;
@@ -221,6 +222,29 @@
void update();
void updateDistributor();
+ protected:
+
+ bool isLevelSensitive(uint32_t int_id) const
+ {
+ return irqConfig[int_id] == Gicv3::INT_LEVEL_SENSITIVE;
+ }
+
+ /**
+ * This helper is used to check if an interrupt should be treated as
+ * edge triggered in the following scenarios:
+ *
+ * a) While activating the interrupt
+ * b) While clearing an interrupt via ICPENDR
+ *
+ * In fact, in these two situations, a level sensitive interrupt
+ * which had been made pending via a write to ISPENDR, will be
+ * treated as it if was edge triggered.
+ */
+ bool treatAsEdgeTriggered(uint32_t int_id) const
+ {
+ return !isLevelSensitive(int_id) || irqPendingIspendr[int_id];
+ }
+
public:
Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
@@ -228,6 +252,7 @@
void init();
uint64_t read(Addr addr, size_t size, bool is_secure_access);
void sendPPInt(uint32_t int_id);
+ void clearPPInt(uint32_t int_id);
void write(Addr addr, uint64_t data, size_t size, bool
is_secure_access);
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Gerrit-Change-Number: 31516
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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