Hello Emily Brickey,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32311
to review the following change.
Change subject: arch: update port terminology
......................................................................
arch: update port terminology
Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d
---
M src/arch/arm/ArmTLB.py
M src/arch/generic/BaseTLB.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/X86LocalApic.py
M src/arch/x86/X86TLB.py
M src/arch/x86/pagetable_walker.hh
7 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 721d062..a821a04 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -54,7 +54,7 @@
# to the Stage2MMU, and shared by the two table walkers, but we
# access it through the ITB and DTB walked objects in the CPU for
# symmetry with the other ISAs.
- port = MasterPort("Port used by the two table walkers")
+ port = RequestPort("Port used by the two table walkers")
sys = Param.System(Parent.any, "system object parameter")
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 02776e6..cca7da6 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -34,4 +34,4 @@
cxx_header = "arch/generic/tlb.hh"
# Ports to connect with other TLB levels
slave = VectorSlavePort("Port closer to the CPU side")
- master = MasterPort("Port closer to memory side")
+ master = RequestPort("Port closer to memory side")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 884b71f..4844feb 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -37,7 +37,7 @@
type = 'RiscvPagetableWalker'
cxx_class = 'RiscvISA::Walker'
cxx_header = 'arch/riscv/pagetable_walker.hh'
- port = MasterPort("Port for the hardware table walker")
+ port = RequestPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
num_squash_per_cycle = Param.Unsigned(4,
"Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/riscv/pagetable_walker.hh
b/src/arch/riscv/pagetable_walker.hh
index 60826a0..d9ab569 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -58,11 +58,11 @@
{
protected:
// Port for accessing memory
- class WalkerPort : public MasterPort
+ class WalkerPort : public RequestPort
{
public:
WalkerPort(const std::string &_name, Walker * _walker) :
- MasterPort(_name, _walker), walker(_walker)
+ RequestPort(_name, _walker), walker(_walker)
{}
protected:
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index a28f6f3..442a5e1 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -48,11 +48,11 @@
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
cxx_header = 'arch/x86/interrupts.hh'
- int_master = MasterPort("Port for sending interrupt messages")
- int_slave = SlavePort("Port for receiving interrupt messages")
+ int_master = RequestPort("Port for sending interrupt messages")
+ int_slave = ResponsePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")
- pio = SlavePort("Programmed I/O port")
+ pio = ResponsePort("Programmed I/O port")
system = Param.System(Parent.any, "System this device is part of")
pio_latency = Param.Latency('100ns', 'Programmed IO latency')
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index bb35526..d9dd980 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -43,7 +43,7 @@
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
cxx_header = 'arch/x86/pagetable_walker.hh'
- port = MasterPort("Port for the hardware table walker")
+ port = RequestPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
num_squash_per_cycle = Param.Unsigned(4,
"Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/x86/pagetable_walker.hh
b/src/arch/x86/pagetable_walker.hh
index a269426..55bb098 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -57,11 +57,11 @@
{
protected:
// Port for accessing memory
- class WalkerPort : public MasterPort
+ class WalkerPort : public RequestPort
{
public:
WalkerPort(const std::string &_name, Walker * _walker) :
- MasterPort(_name, _walker), walker(_walker)
+ RequestPort(_name, _walker), walker(_walker)
{}
protected:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32311
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d
Gerrit-Change-Number: 32311
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-Reviewer: Emily Brickey <esbric...@ucdavis.edu>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
