Hello John Alsop,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32602
to review the following change.
Change subject: mem-ruby: make simplenetwork compatible with garnet3.0
topologies
......................................................................
mem-ruby: make simplenetwork compatible with garnet3.0 topologies
1) To support controllers with multiple outgoing links (added
in garnet 3.0), only connect a message buffer to a controller
if the vnet in that message buffer matches the
vnets assigned to the link. This is needed to support controllers
with multiple outgoing links (added in garnet 3.0).
Similarly, a separate routing table must be managed for each vnet
at each simple network router.
2) Dummy parameters must be added for garnet-specific members
in network base classes to prevent errors.
Change-Id: I78cfce99edf73cd647c05ef7a3a619218493d9de
---
M src/mem/ruby/network/BasicLink.py
M src/mem/ruby/network/garnet2.0/GarnetLink.py
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.py
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
8 files changed, 63 insertions(+), 30 deletions(-)
diff --git a/src/mem/ruby/network/BasicLink.py
b/src/mem/ruby/network/BasicLink.py
index 2718aa6..b9ded1f 100644
--- a/src/mem/ruby/network/BasicLink.py
+++ b/src/mem/ruby/network/BasicLink.py
@@ -39,6 +39,16 @@
weight = Param.Int(1, "used to restrict routing in shortest path
analysis")
supported_vnets = VectorParam.Int([-1], "Vnets supported
Default:All(-1)")
+ # dummy variables for compatibility with garnet topology
+ ext_cdc = Param.Bool(False, "Dummy")
+ int_cdc = Param.Bool(False, "Dummy")
+ ext_serdes = Param.Bool(False, "Dummy")
+ int_serdes = Param.Bool(False, "Dummy")
+ src_serdes = Param.Bool(False, "Dummy")
+ dst_serdes = Param.Bool(False, "Dummy")
+ width = Param.UInt32(0, "Dummy")
+ vcs_per_vnet = Param.Int(0, "Dummy")
+
class BasicExtLink(BasicLink):
type = 'BasicExtLink'
cxx_header = "mem/ruby/network/BasicLink.hh"
@@ -46,6 +56,12 @@
int_node = Param.BasicRouter("ID of internal node")
bandwidth_factor = 16 # only used by simple network
+ # only used by Garnet.
+ ext_cdc = Param.Bool(False, "Enable CDC")
+ int_cdc = Param.Bool(False, "Enable CDC")
+ ext_serdes = Param.Bool(False, "Enable CDC")
+ int_serdes = Param.Bool(False, "Enable CDC")
+
class BasicIntLink(BasicLink):
type = 'BasicIntLink'
cxx_header = "mem/ruby/network/BasicLink.hh"
@@ -55,6 +71,10 @@
# only used by Garnet.
src_outport = Param.String("", "Outport direction at src router")
dst_inport = Param.String("", "Inport direction at dst router")
+ src_cdc = Param.Bool(False, "Enable CDC")
+ dst_cdc = Param.Bool(False, "Enable CDC")
+ src_serdes = Param.Bool(False, "Enable CDC")
+ dst_serdes = Param.Bool(False, "Enable CDC")
# only used by simple network
bandwidth_factor = 16
diff --git a/src/mem/ruby/network/garnet2.0/GarnetLink.py
b/src/mem/ruby/network/garnet2.0/GarnetLink.py
index 769680c..f356d97 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetLink.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetLink.py
@@ -64,17 +64,11 @@
network_link = Param.NetworkLink(NetworkLink(), "forward link")
credit_link = Param.CreditLink(CreditLink(), "backward flow-control
link")
- src_cdc = Param.Bool(False, "Enable CDC")
- dst_cdc = Param.Bool(False, "Enable CDC")
-
src_net_bridge = Param.NetworkBridge("Network CDC at source")
dst_net_bridge = Param.NetworkBridge("Network CDC at dest")
src_cred_bridge = Param.NetworkBridge("Credit CDC at source")
dst_cred_bridge = Param.NetworkBridge("Credit CDC at dest")
- src_serdes = Param.Bool(False, "Enable CDC")
- dst_serdes = Param.Bool(False, "Enable CDC")
-
width = Param.UInt32(Parent.ni_flit_size,
"bit width supported by the router")
@@ -100,16 +94,10 @@
_cls.append(CreditLink());
credit_links = VectorParam.CreditLink(_cls, "backward flow-control
links")
- ext_cdc = Param.Bool(False, "Enable CDC")
- int_cdc = Param.Bool(False, "Enable CDC")
-
ext_net_bridge = VectorParam.NetworkBridge("CDC to reach the
consumers")
ext_cred_bridge = VectorParam.NetworkBridge("CDC to reach the
consumers")
int_net_bridge = VectorParam.NetworkBridge("CDC to reach the
consumers")
int_cred_bridge = VectorParam.NetworkBridge("CDC to reach the
consumers")
- ext_serdes = Param.Bool(False, "Enable CDC")
- int_serdes = Param.Bool(False, "Enable CDC")
-
width = Param.UInt32(Parent.ni_flit_size,
"bit width supported by the router")
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 156b96d..e46e5e3 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -68,13 +68,14 @@
}
void
-PerfectSwitch::addInPort(const vector<MessageBuffer*>& in)
+PerfectSwitch::addInPort(const vector<MessageBuffer*>& in, int vnet=-1)
{
NodeID port = m_in.size();
m_in.push_back(in);
for (int i = 0; i < in.size(); ++i) {
- if (in[i] != nullptr) {
+ if (in[i] != nullptr &&
+ (vnet==-1 || i==vnet)) {
in[i]->setConsumer(this);
in[i]->setIncomingLink(port);
in[i]->setVnet(i);
@@ -84,7 +85,7 @@
void
PerfectSwitch::addOutPort(const vector<MessageBuffer*>& out,
- const NetDest& routing_table_entry)
+ std::vector<NetDest>& routing_table_entry)
{
// Setup link order
LinkOrder l;
@@ -94,7 +95,11 @@
// Add to routing table
m_out.push_back(out);
- m_routing_table.push_back(routing_table_entry);
+ NetDest all_link_dsts;
+ for (int v = 0; v < routing_table_entry.size(); v++) {
+ all_link_dsts = all_link_dsts.OR(routing_table_entry[v]);
+ }
+ m_routing_table.push_back(all_link_dsts);
}
PerfectSwitch::~PerfectSwitch()
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index 12d5e46..2f7deff 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -66,9 +66,9 @@
{ return csprintf("PerfectSwitch-%i", m_switch_id); }
void init(SimpleNetwork *);
- void addInPort(const std::vector<MessageBuffer*>& in);
+ void addInPort(const std::vector<MessageBuffer*>& in, int vnet);
void addOutPort(const std::vector<MessageBuffer*>& out,
- const NetDest& routing_table_entry);
+ std::vector<NetDest>& routing_table_entry);
int getInLinks() const { return m_in.size(); }
int getOutLinks() const { return m_out.size(); }
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index edffc3d..623ecbe 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -96,7 +96,8 @@
SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
- routing_table_entry[0],
simple_link->m_latency,
+ routing_table_entry,
+ simple_link->m_latency,
simple_link->m_bw_multiplier);
}
@@ -107,7 +108,15 @@
{
NodeID local_src = getLocalNodeID(global_src);
assert(local_src < m_nodes);
- m_switches[dest]->addInPort(m_toNetQueues[local_src]);
+ // only connect this switch/link to message buffers with matching vnets
+ if (link->mVnets[0]==-1) {
+ m_switches[dest]->addInPort(m_toNetQueues[local_src], -1);
+ } else {
+ for (int v = 0; v < link->mVnets.size(); v++) {
+ m_switches[dest]->addInPort(m_toNetQueues[local_src],
+ link->mVnets[v]);
+ }
+ }
}
// From a switch to a switch
@@ -131,10 +140,17 @@
// Connect it to the two switches
SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
- m_switches[dest]->addInPort(queues);
- m_switches[src]->addOutPort(queues, routing_table_entry[0],
- simple_link->m_latency,
- simple_link->m_bw_multiplier);
+ // only connect this switch/link to message buffers with matching vnets
+ if (link->mVnets[0]==-1) {
+ m_switches[dest]->addInPort(queues, -1);
+ } else {
+ for (int v = 0; v < link->mVnets.size(); v++) {
+ m_switches[dest]->addInPort(queues, link->mVnets[v]);
+ }
+ }
+ m_switches[src]->addOutPort(queues, routing_table_entry,
+ simple_link->m_latency,
+ simple_link->m_bw_multiplier);
}
void
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py
b/src/mem/ruby/network/simple/SimpleNetwork.py
index b4fd81f..97c94b3 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -39,6 +39,8 @@
endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor");
adaptive_routing = Param.Bool(False, "enable adaptive routing");
int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links")
+ # dummy param for garnet compatibility
+ vcs_per_vnet = Param.Int(0, "Dummy")
def setup_buffers(self):
# Note that all SimpleNetwork MessageBuffers are currently ordered
@@ -64,7 +66,7 @@
# Add message buffers to routers for each external link
connection
for link in self.ext_links:
# Routers can only be int_nodes on ext_links
- if link.int_node in self.routers:
+ if link.int_node == router:
for i in range(int(self.number_of_virtual_networks)):
router_buffers.append(MessageBuffer(ordered =
True))
router.port_buffers = router_buffers
@@ -75,3 +77,5 @@
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
port_buffers = VectorParam.MessageBuffer("Port buffers")
+ # dummy param for garnet compatibility
+ vcs_per_vnet = Param.Int(0, "Dummy")
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index d1e5026..ffe3da3 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -69,14 +69,14 @@
}
void
-Switch::addInPort(const vector<MessageBuffer*>& in)
+Switch::addInPort(const vector<MessageBuffer*>& in, int vnet=-1)
{
- perfectSwitch.addInPort(in);
+ perfectSwitch.addInPort(in, vnet);
}
void
Switch::addOutPort(const vector<MessageBuffer*>& out,
- const NetDest& routing_table_entry,
+ std::vector<NetDest>& routing_table_entry,
Cycles link_latency, int bw_multiplier)
{
// Create a throttle
diff --git a/src/mem/ruby/network/simple/Switch.hh
b/src/mem/ruby/network/simple/Switch.hh
index 5d26906..60a0185 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -64,9 +64,9 @@
~Switch() = default;
void init();
- void addInPort(const std::vector<MessageBuffer*>& in);
+ void addInPort(const std::vector<MessageBuffer*>& in, int vnet);
void addOutPort(const std::vector<MessageBuffer*>& out,
- const NetDest& routing_table_entry,
+ std::vector<NetDest>& routing_table_entry,
Cycles link_latency, int bw_multiplier);
void resetStats();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32602
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I78cfce99edf73cd647c05ef7a3a619218493d9de
Gerrit-Change-Number: 32602
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj <srikant.bharad...@amd.com>
Gerrit-Reviewer: John Alsop <johnathan.al...@amd.com>
Gerrit-MessageType: newchange
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