Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32636
to review the following change.
Change subject: arch-arm: Disable HVC when SCR_EL3.HCE is 0
......................................................................
arch-arm: Disable HVC when SCR_EL3.HCE is 0
This was already implemented for AArch32 but it had been wrongly
removed by:
https://gem5-review.googlesource.com/c/public/gem5/+/31394
Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
---
M src/arch/arm/isa/insts/misc.isa
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 3ee0d61..5439baa 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -119,12 +119,15 @@
exec_output += PredOpExecute.subst(smcIop)
hvcCode = '''
+ HCR hcr = Hcr;
CPSR cpsr = Cpsr;
+ SCR scr = Scr;
// Filter out the various cases where this instruction isn't defined
if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
(cpsr.mode == MODE_USER) ||
- (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase()))) {
+ (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) ||
+ (ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) {
fault = disabledFault();
} else {
fault = std::make_shared<HypervisorCall>(machInst, imm);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32636
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Gerrit-Change-Number: 32636
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: newchange
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