Srikant Bharadwaj has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32681 )
Change subject: mem-garnet: Add example Mesh topologies exercising
HeteroGarnet
......................................................................
mem-garnet: Add example Mesh topologies exercising HeteroGarnet
This patch adds two new topologies which show the use cases
of HeteroGarnet. Users can start building their topologies
using these example topologies.
Change-Id: I655aa673b0de8436c4930e68861a703edf2320ec
---
A configs/topologies/Mesh_SerDes.py
A configs/topologies/Mesh_VF.py
2 files changed, 515 insertions(+), 0 deletions(-)
diff --git a/configs/topologies/Mesh_SerDes.py
b/configs/topologies/Mesh_SerDes.py
new file mode 100644
index 0000000..db31840
--- /dev/null
+++ b/configs/topologies/Mesh_SerDes.py
@@ -0,0 +1,249 @@
+# Copyright (c) 2020 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Srikant Bharadwaj
+
+
+from m5.params import *
+from m5.objects import *
+
+from BaseTopology import SimpleTopology
+
+# Creates a generic Mesh assuming an equal number of cache
+# and directory controllers.
+# XY routing is enforced (using link weights)
+# to guarantee deadlock freedom.
+
+class Mesh_SerDes(SimpleTopology):
+ description='Mesh_SerDes'
+
+ def __init__(self, controllers):
+ self.nodes = controllers
+
+ # Makes a generic mesh
+ # assuming an equal number of cache and directory cntrls
+
+ def makeTopology(self, options, network, IntLink, ExtLink, Router):
+ nodes = self.nodes
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ # default values for link latency and router latency.
+ # Can be over-ridden on a per link/router basis
+ link_latency = options.link_latency # used by simple and garnet
+ router_latency = options.router_latency # only used by garnet
+
+
+ # There must be an evenly divisible number of cntrls to routers
+ # Also, obviously the number or rows must be <= the number of
routers
+ cntrls_per_router, remainder = divmod(len(nodes), num_routers)
+ assert(num_rows > 0 and num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+
+ # This topology is supported only for a 4x4 mesh
+ assert(num_rows == 4 and num_columns == 4)
+
+ # Create the routers in the mesh
+ routers = [Router(router_id=i, latency = router_latency) \
+ for i in range(num_routers)]
+ network.routers = routers
+
+ # link counter to set unique link ids
+ link_count = 0
+
+ # Add all but the remainder nodes to the list of nodes to be
uniformly
+ # distributed across the network.
+ network_nodes = []
+ remainder_nodes = []
+ for node_index in xrange(len(nodes)):
+ if node_index < (len(nodes) - remainder):
+ network_nodes.append(nodes[node_index])
+ else:
+ remainder_nodes.append(nodes[node_index])
+
+ # We create a Mesh of routers with 4 routers supporting 32B flits
+ # and rest supporting 64B. The four 32B routers will have a
+ # SerDes on the internal end of the external link. So the network
+ # interfaces will always recieve 64B flits in this example.
+
+ # Connect each node to the appropriate router
+ ext_links = []
+ for (i, n) in enumerate(network_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < cntrls_per_router)
+ lWidth = 64
+ rWidth = 64
+ intSD = False
+ if (router_id == 5) or (router_id == 6) or \
+ (router_id == 9) or (router_id == 10):
+ rWidth = 32
+ intSD = True
+ routers[router_id].width = rWidth
+ ext_links.append(ExtLink(link_id=link_count, ext_node=n,
+ int_node=routers[router_id],
+ width=lWidth,
+ int_serdes = intSD,
+ latency = link_latency))
+ link_count += 1
+
+ # Connect the remainding nodes to router 0. These should only be
+ # DMA nodes.
+ for (i, node) in enumerate(remainder_nodes):
+ assert(node.type == 'DMA_Controller')
+ assert(i < remainder)
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[0],
+ latency = link_latency))
+ link_count += 1
+
+ network.ext_links = ext_links
+
+ # Create the mesh links.
+ int_links = []
+
+ # East output to West input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ srcSD = False
+ dstSD = False
+ bwidth = 64
+ if (row == 1) or (row == 2):
+ if (col == 0):
+ dstSD = True
+ elif (col == 1):
+ dstSD = True
+ srcSD = True
+ elif (col == 2):
+ srcSD = True
+ east_out = col + (row * num_columns)
+ west_in = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[east_out],
+ dst_node=routers[west_in],
+ src_outport="East",
+ dst_inport="West",
+ src_serdes = srcSD,
+ dst_serdes = dstSD,
+ width = bwidth,
+ latency = link_latency,
+ weight=1))
+ link_count += 1
+
+ # West output to East input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ srcSD = False
+ dstSD = False
+ bwidth = 64
+ if (row == 1) or (row == 2):
+ if (col == 2):
+ dstSD = True
+ elif (col == 1):
+ dstSD = True
+ srcSD = True
+ elif (col == 0):
+ srcSD = True
+ east_in = col + (row * num_columns)
+ west_out = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[west_out],
+ dst_node=routers[east_in],
+ src_outport="West",
+ dst_inport="East",
+ src_serdes = srcSD,
+ dst_serdes = dstSD,
+ width = bwidth,
+ latency = link_latency,
+ weight=1))
+ link_count += 1
+
+ # North output to South input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ srcSD = False
+ dstSD = False
+ bwidth = 64
+ if (col == 1) or (col == 2):
+ if (row == 0):
+ dstSD = True
+ elif (row == 1):
+ bwidth = 32
+ elif (row == 2):
+ srcSD = True
+ north_out = col + (row * num_columns)
+ south_in = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[north_out],
+ dst_node=routers[south_in],
+ src_outport="North",
+ dst_inport="South",
+ src_serdes = srcSD,
+ dst_serdes = dstSD,
+ width = bwidth,
+ latency = link_latency,
+ weight=2))
+ link_count += 1
+
+ # South output to North input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ srcSD = False
+ dstSD = False
+ bwidth = 64
+ if (col == 1) or (col == 2):
+ if (row == 2):
+ dstSD = True
+ elif (row == 1):
+ bwidth = 32
+ elif (row == 0):
+ srcSD = True
+ north_in = col + (row * num_columns)
+ south_out = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[south_out],
+ dst_node=routers[north_in],
+ src_outport="South",
+ dst_inport="North",
+ src_serdes = srcSD,
+ dst_serdes = dstSD,
+ width = bwidth,
+ latency = link_latency,
+ weight=2))
+ link_count += 1
+
+
+ network.int_links = int_links
diff --git a/configs/topologies/Mesh_VF.py b/configs/topologies/Mesh_VF.py
new file mode 100644
index 0000000..34e4ed1
--- /dev/null
+++ b/configs/topologies/Mesh_VF.py
@@ -0,0 +1,266 @@
+# Copyright (c) 2020 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Srikant Bharadwaj
+
+
+from m5.params import *
+from m5.objects import *
+
+from BaseTopology import SimpleTopology
+
+# Creates a generic Mesh assuming an equal number of cache
+# and directory controllers.
+# XY routing is enforced (using link weights)
+# to guarantee deadlock freedom.
+
+class Mesh_VF(SimpleTopology):
+ description='Mesh_VF'
+
+ def __init__(self, controllers):
+ self.nodes = controllers
+
+ # Makes a generic mesh
+ # assuming an equal number of cache and directory cntrls
+
+ def makeTopology(self, options, network, IntLink, ExtLink, Router):
+ nodes = self.nodes
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ # default values for link latency and router latency.
+ # Can be over-ridden on a per link/router basis
+ link_latency = options.link_latency # used by simple and garnet
+ router_latency = options.router_latency # only used by garnet
+
+ # We create a Mesh network with some units operating at
+ # a slower clock domain and other units operating at a
+ # faster clock domain
+ slow_freq = '2.0GHz'
+ fast_freq = '3.0GHz'
+
+ # There must be an evenly divisible number of cntrls to routers
+ # Also, obviously the number or rows must be <= the number of
routers
+ cntrls_per_router, remainder = divmod(len(nodes), num_routers)
+ assert(num_rows > 0 and num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+
+ # Create the routers in the mesh
+ routers = [Router(router_id=i, latency = router_latency) \
+ for i in range(num_routers)]
+ network.routers = routers
+
+ # link counter to set unique link ids
+ link_count = 0
+
+ # Add all but the remainder nodes to the list of nodes to be
uniformly
+ # distributed across the network.
+ network_nodes = []
+ remainder_nodes = []
+ for node_index in xrange(len(nodes)):
+ if node_index < (len(nodes) - remainder):
+ network_nodes.append(nodes[node_index])
+ else:
+ remainder_nodes.append(nodes[node_index])
+
+ # Connect each node to the appropriate router
+ ext_links = []
+ for (i, n) in enumerate(network_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < cntrls_per_router)
+ intCDC = False
+ router_freq = slow_freq
+ if (router_id == 5) or (router_id == 6) or \
+ (router_id == 9) or (router_id == 10):
+ router_freq = fast_freq
+ intCDC = True
+ router_clk = SrcClockDomain(clock = router_freq,
+ voltage_domain = VoltageDomain(
+ voltage = options.sys_voltage))
+ routers[router_id].clk_domain = router_clk
+ ext_links.append(ExtLink(link_id=link_count, ext_node=n,
+ int_node=routers[router_id],
+ int_cdc = intCDC,
+ latency = link_latency))
+ link_count += 1
+
+ # Connect the remainding nodes to router 0. These should only be
+ # DMA nodes.
+ for (i, node) in enumerate(remainder_nodes):
+ assert(node.type == 'DMA_Controller')
+ assert(i < remainder)
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[0],
+ latency = link_latency))
+ link_count += 1
+
+ network.ext_links = ext_links
+
+ # Create the mesh links.
+ int_links = []
+
+ # East output to West input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ srcCDC = False
+ dstCDC = False
+ link_freq = slow_freq
+ if (row == 1) or (row == 2):
+ if (col == 0):
+ dstCDC = True
+ elif (col == 1):
+ dstCDC = True
+ srcCDC = True
+ elif (col == 2):
+ srcCDC = True
+ east_out = col + (row * num_columns)
+ west_in = (col + 1) + (row * num_columns)
+
+ link_clk = SrcClockDomain(clock = link_freq,
+ voltage_domain = VoltageDomain(
+ voltage = options.sys_voltage))
+
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[east_out],
+ dst_node=routers[west_in],
+ src_outport="East",
+ dst_inport="West",
+ src_cdc = srcCDC,
+ dst_cdc = dstCDC,
+ clk_domain = link_clk,
+ latency = link_latency,
+ weight=1))
+ link_count += 1
+
+ # West output to East input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ srcCDC = False
+ dstCDC = False
+ link_freq = slow_freq
+ if (row == 1) or (row == 2):
+ if (col == 2):
+ dstCDC = True
+ elif (col == 1):
+ dstCDC = True
+ srcCDC = True
+ elif (col == 0):
+ srcCDC = True
+ east_in = col + (row * num_columns)
+ west_out = (col + 1) + (row * num_columns)
+
+ link_clk = SrcClockDomain(clock = link_freq,
+ voltage_domain = VoltageDomain(
+ voltage = options.sys_voltage))
+
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[west_out],
+ dst_node=routers[east_in],
+ src_outport="West",
+ dst_inport="East",
+ src_cdc = srcCDC,
+ dst_cdc = dstCDC,
+ clk_domain = link_clk,
+ latency = link_latency,
+ weight=1))
+ link_count += 1
+
+ # North output to South input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ srcCDC = False
+ dstCDC = False
+ link_freq = slow_freq
+ if (col == 1) or (col == 2):
+ if (row == 0):
+ dstCDC = True
+ elif (row == 1):
+ link_freq = fast_freq
+ elif (row == 2):
+ srcCDC = True
+ north_out = col + (row * num_columns)
+ south_in = col + ((row + 1) * num_columns)
+
+ link_clk = SrcClockDomain(clock = link_freq,
+ voltage_domain = VoltageDomain(
+ voltage = options.sys_voltage))
+
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[north_out],
+ dst_node=routers[south_in],
+ src_outport="North",
+ dst_inport="South",
+ src_cdc = srcCDC,
+ dst_cdc = dstCDC,
+ clk_domain = link_clk,
+ latency = link_latency,
+ weight=2))
+ link_count += 1
+
+ # South output to North input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ srcCDC = False
+ dstCDC = False
+ link_freq = slow_freq
+ if (col == 1) or (col == 2):
+ if (row == 2):
+ dstCDC = True
+ elif (row == 1):
+ link_freq = fast_freq
+ elif (row == 0):
+ srcCDC = True
+ north_in = col + (row * num_columns)
+ south_out = col + ((row + 1) * num_columns)
+
+ link_clk = SrcClockDomain(clock = link_freq,
+ voltage_domain = VoltageDomain(
+ voltage = options.sys_voltage))
+
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[south_out],
+ dst_node=routers[north_in],
+ src_outport="South",
+ dst_inport="North",
+ src_cdc = srcCDC,
+ dst_cdc = dstCDC,
+ clk_domain = link_clk,
+ latency = link_latency,
+ weight=2))
+ link_count += 1
+
+ network.int_links = int_links
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I655aa673b0de8436c4930e68861a703edf2320ec
Gerrit-Change-Number: 32681
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj <[email protected]>
Gerrit-MessageType: newchange
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