Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32814 )
Change subject: arch-riscv: Fix disassembling of CSR instructions
......................................................................
arch-riscv: Fix disassembling of CSR instructions
The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm
This patch fixes the problem.
Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/insts/standard.cc
1 file changed, 5 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index 9a9aa9d..35f9ccd 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,13 +60,15 @@
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
- if (_numSrcRegs > 0)
- ss << registerName(_srcRegIdx[0]) << ", ";
auto data = CSRData.find(csr);
if (data != CSRData.end())
ss << data->second.name;
else
- ss << "?? (" << hex << "0x" << csr << ")";
+ ss << "?? (" << hex << "0x" << csr << dec << ")";
+ if (_numSrcRegs > 0)
+ ss << ", " << registerName(_srcRegIdx[0]);
+ else
+ ss << uimm;
return ss.str();
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Gerrit-Change-Number: 32814
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Ian Jiang <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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