Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32914 )
Change subject: tests: Removed the hello tests from .testignore
......................................................................
tests: Removed the hello tests from .testignore
The "hello" tests that were previously ignored are all functioning
correctly, and are therefore being re-included in the test suite. The
MIPS and SPARC tests have been tagged a "long" as we do not compile
these ISAs are part of our "quick" tests.
Change-Id: I3aa079b81b938a12da6993213d158e53bc4ae514
---
M tests/gem5/.testignore
M tests/gem5/hello_se/test_hello_se.py
2 files changed, 11 insertions(+), 54 deletions(-)
diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index 405f005..b450fc0 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -92,60 +92,6 @@
test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-fast
test-insttest-linux-AtomicSimpleCPU-SPARC-i386-fast
test-insttest-linux-TimingSimpleCPU-SPARC-i386-fast
-test-hello-linux-MinorCPU-RISCV-x86_64-debug
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-debug
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-debug
-test-hello-linux-DerivO3CPU-MIPS-x86_64-debug
-test-hello-linux-MinorCPU-RISCV-x86_64-fast
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-fast
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-fast
-test-hello-linux-DerivO3CPU-MIPS-x86_64-fast
-test-hello-linux-MinorCPU-RISCV-x86_64-opt
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-opt
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt
-test-hello-linux-DerivO3CPU-MIPS-x86_64-opt
-test-hello-linux-MinorCPU-RISCV-aarch64-debug
-test-hello-linux-TimingSimpleCPU-SPARC-aarch64-debug
-test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-debug
-test-hello-linux-TimingSimpleCPU-MIPS-aarch64-debug
-test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-debug
-test-hello-linux-DerivO3CPU-MIPS-aarch64-debug
-test-hello-linux-MinorCPU-RISCV-aarch64-fast
-test-hello-linux-TimingSimpleCPU-SPARC-aarch64-fast
-test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-fast
-test-hello-linux-TimingSimpleCPU-MIPS-aarch64-fast
-test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-fast
-test-hello-linux-DerivO3CPU-MIPS-aarch64-fast
-test-hello-linux-MinorCPU-RISCV-aarch64-opt
-test-hello-linux-TimingSimpleCPU-SPARC-aarch64-opt
-test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-opt
-test-hello-linux-TimingSimpleCPU-MIPS-aarch64-opt
-test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-opt
-test-hello-linux-DerivO3CPU-MIPS-aarch64-opt
-test-hello-linux-MinorCPU-RISCV-i386-debug
-test-hello-linux-TimingSimpleCPU-SPARC-i386-debug
-test-hello-linux-AtomicSimpleCPU-SPARC-i386-debug
-test-hello-linux-TimingSimpleCPU-MIPS-i386-debug
-test-hello-linux-AtomicSimpleCPU-MIPS-i386-debug
-test-hello-linux-DerivO3CPU-MIPS-i386-debug
-test-hello-linux-MinorCPU-RISCV-i386-fast
-test-hello-linux-TimingSimpleCPU-SPARC-i386-fast
-test-hello-linux-AtomicSimpleCPU-SPARC-i386-fast
-test-hello-linux-TimingSimpleCPU-MIPS-i386-fast
-test-hello-linux-AtomicSimpleCPU-MIPS-i386-fast
-test-hello-linux-DerivO3CPU-MIPS-i386-fast
-test-hello-linux-MinorCPU-RISCV-i386-opt
-test-hello-linux-TimingSimpleCPU-SPARC-i386-opt
-test-hello-linux-AtomicSimpleCPU-SPARC-i386-opt
-test-hello-linux-TimingSimpleCPU-MIPS-i386-opt
-test-hello-linux-AtomicSimpleCPU-MIPS-i386-opt
-test-hello-linux-DerivO3CPU-MIPS-i386-opt
test-atomic-DerivO3CPU-SPARC-x86_64-opt
test-atomic-TimingSimpleCPU-SPARC-x86_64-opt
test-atomic-DerivO3CPU-SPARC-x86_64-debug
diff --git a/tests/gem5/hello_se/test_hello_se.py
b/tests/gem5/hello_se/test_hello_se.py
index 96f6d33..c7cf7fe 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -72,6 +72,16 @@
'sparc' : ('linux',)
}
+# We only want to test x86, arm, and riscv on quick. Mips and sparc will be
+# left for long.
+os_length = {
+ 'x86': constants.quick_tag,
+ 'arm' : constants.quick_tag,
+ 'mips' : constants.long_tag,
+ 'riscv' : constants.quick_tag,
+ 'sparc' : constants.long_tag,
+}
+
if config.bin_path:
base_path = config.bin_path
else:
@@ -99,6 +109,7 @@
'--caches'],
valid_isas=(isa.upper(),),
valid_hosts=hosts,
+ length = os_length[isa],
)
# Run statically linked hello worlds
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32914
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3aa079b81b938a12da6993213d158e53bc4ae514
Gerrit-Change-Number: 32914
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce <[email protected]>
Gerrit-MessageType: newchange
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