Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33015 )
Change subject: tests: ignore 32-bit arm dual linux boot tests
......................................................................
tests: ignore 32-bit arm dual linux boot tests
As mentioned on the JIRA issue, uncacheable requests done after
cacheable requests had been done to the address make the cache writeback
and write trash data to memory.
We believe that the kernel must be doing earlier invalidation by set and
way earlier on to prevent this, but that is not implemented in gem5 yet.
The problem can be worked around by booting in atomic without caches and
checkpointing after init, because uncacheable accesses are only done on
early stages of CPU bringup, which is the more common use case anyways.
The aarch64 Linux kernel developers have stated that set and way
invalidates are not going to be used in aarch64, which further reduces the
importance of implementing this immediatly
JIRA: https://gem5.atlassian.net/browse/GEM5-640
Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
---
M tests/gem5/.testignore
1 file changed, 5 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index 08afde7..6228ad2 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -1,4 +1,9 @@
+realview-minor-dual-ARM-x86_64-opt
realview-o3-checker-ARM-x86_64-opt
+realview-o3-dual-ARM-x86_64-opt
+realview-simple-atomic-dual-ARM-x86_64-opt
+realview-simple-timing-dual-ARM-x86_64-opt
+realview-simple-timing-dual-ruby-ARM-x86_64-opt
realview64-o3-checker-ARM-x86_64-opt
test-atomic-DerivO3CPU-SPARC-aarch64-debug
test-atomic-DerivO3CPU-SPARC-aarch64-fast
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Gerrit-Change-Number: 33015
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <[email protected]>
Gerrit-MessageType: newchange
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