Emily Brickey has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32835 )
Change subject: arch-riscv, arch-x86: convert tlb to new style stats
......................................................................
arch-riscv, arch-x86: convert tlb to new style stats
Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32835
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
4 files changed, 56 insertions(+), 110 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index c8b1a4c..34ccc03 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -66,7 +66,7 @@
}
TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), tlb(size), lruSeq(0)
+ : BaseTLB(p), size(p->size), tlb(size), lruSeq(0), stats(this)
{
for (size_t x = 0; x < size; x++) {
tlb[x].trieHandle = NULL;
@@ -108,21 +108,21 @@
entry->lruSeq = nextSeq();
if (mode == Write)
- write_accesses++;
+ stats.write_accesses++;
else
- read_accesses++;
+ stats.read_accesses++;
if (!entry) {
if (mode == Write)
- write_misses++;
+ stats.write_misses++;
else
- read_misses++;
+ stats.read_misses++;
}
else {
if (mode == Write)
- write_hits++;
+ stats.write_hits++;
else
- read_hits++;
+ stats.read_hits++;
}
DPRINTF(TLBVerbose, "lookup(vpn=%#x, asid=%#x): %s ppn %#x\n",
@@ -496,61 +496,20 @@
}
}
-void
-TLB::regStats()
+TLB::TlbStats::TlbStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ ADD_STAT(read_hits, "read hits"),
+ ADD_STAT(read_misses, "read misses"),
+ ADD_STAT(read_accesses, "read accesses"),
+ ADD_STAT(write_hits, "write hits"),
+ ADD_STAT(write_misses, "write misses"),
+ ADD_STAT(write_accesses, "write accesses"),
+ ADD_STAT(hits, "Total TLB (read and write) hits", read_hits +
write_hits),
+ ADD_STAT(misses, "Total TLB (read and write) misses",
+ read_misses + write_misses),
+ ADD_STAT(accesses, "Total TLB (read and write) accesses",
+ read_accesses + write_accesses)
{
- BaseTLB::regStats();
-
- read_hits
- .name(name() + ".read_hits")
- .desc("DTB read hits")
- ;
-
- read_misses
- .name(name() + ".read_misses")
- .desc("DTB read misses")
- ;
-
-
- read_accesses
- .name(name() + ".read_accesses")
- .desc("DTB read accesses")
- ;
-
- write_hits
- .name(name() + ".write_hits")
- .desc("DTB write hits")
- ;
-
- write_misses
- .name(name() + ".write_misses")
- .desc("DTB write misses")
- ;
-
-
- write_accesses
- .name(name() + ".write_accesses")
- .desc("DTB write accesses")
- ;
-
- hits
- .name(name() + ".hits")
- .desc("DTB hits")
- ;
-
- misses
- .name(name() + ".misses")
- .desc("DTB misses")
- ;
-
- accesses
- .name(name() + ".accesses")
- .desc("DTB accesses")
- ;
-
- hits = read_hits + write_hits;
- misses = read_misses + write_misses;
- accesses = read_accesses + write_accesses;
}
RiscvISA::TLB *
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 7ed6628..a92bdd2 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -52,7 +52,7 @@
class Walker;
class TLB : public BaseTLB
-{
+ {
typedef std::list<TlbEntry *> EntryList;
protected:
@@ -64,17 +64,22 @@
Walker *walker;
- mutable Stats::Scalar read_hits;
- mutable Stats::Scalar read_misses;
- mutable Stats::Scalar read_acv;
- mutable Stats::Scalar read_accesses;
- mutable Stats::Scalar write_hits;
- mutable Stats::Scalar write_misses;
- mutable Stats::Scalar write_acv;
- mutable Stats::Scalar write_accesses;
- Stats::Formula hits;
- Stats::Formula misses;
- Stats::Formula accesses;
+ struct TlbStats : public Stats::Group{
+ TlbStats(Stats::Group *parent);
+
+ Stats::Scalar read_hits;
+ Stats::Scalar read_misses;
+ Stats::Scalar read_acv;
+ Stats::Scalar read_accesses;
+ Stats::Scalar write_hits;
+ Stats::Scalar write_misses;
+ Stats::Scalar write_acv;
+ Stats::Scalar write_accesses;
+
+ Stats::Formula hits;
+ Stats::Formula misses;
+ Stats::Formula accesses;
+ } stats;
public:
typedef RiscvTLBParams Params;
@@ -98,8 +103,6 @@
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void regStats() override;
-
Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode);
Fault translateAtomic(const RequestPtr &req,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 4e9d4be..11ce660 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -61,7 +61,7 @@
TLB::TLB(const Params *p)
: BaseTLB(p), configAddress(0), size(p->size),
- tlb(size), lruSeq(0), m5opRange(p->system->m5opRange())
+ tlb(size), lruSeq(0), m5opRange(p->system->m5opRange()), stats(this)
{
if (!size)
fatal("TLBs must have a non-zero size.\n");
@@ -373,18 +373,18 @@
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (mode == Read) {
- rdAccesses++;
+ stats.rdAccesses++;
} else {
- wrAccesses++;
+ stats.wrAccesses++;
}
if (!entry) {
DPRINTF(TLB, "Handling a TLB miss for "
"address %#x at pc %#x.\n",
vaddr, tc->instAddr());
if (mode == Read) {
- rdMisses++;
+ stats.rdMisses++;
} else {
- wrMisses++;
+ stats.wrMisses++;
}
if (FullSystem) {
Fault fault = walker->start(tc, translation, req,
mode);
@@ -518,27 +518,13 @@
return walker;
}
-void
-TLB::regStats()
+TLB::TlbStats::TlbStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ ADD_STAT(rdAccesses, "TLB accesses on read requests"),
+ ADD_STAT(wrAccesses, "TLB accesses on write requests"),
+ ADD_STAT(rdMisses, "TLB misses on read requests"),
+ ADD_STAT(wrMisses, "TLB misses on write requests")
{
- using namespace Stats;
- BaseTLB::regStats();
- rdAccesses
- .name(name() + ".rdAccesses")
- .desc("TLB accesses on read requests");
-
- wrAccesses
- .name(name() + ".wrAccesses")
- .desc("TLB accesses on write requests");
-
- rdMisses
- .name(name() + ".rdMisses")
- .desc("TLB misses on read requests");
-
- wrMisses
- .name(name() + ".wrMisses")
- .desc("TLB misses on write requests");
-
}
void
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 2a8cabf..671b165 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -101,11 +101,14 @@
AddrRange m5opRange;
- // Statistics
- Stats::Scalar rdAccesses;
- Stats::Scalar wrAccesses;
- Stats::Scalar rdMisses;
- Stats::Scalar wrMisses;
+ struct TlbStats : public Stats::Group {
+ TlbStats(Stats::Group *parent);
+
+ Stats::Scalar rdAccesses;
+ Stats::Scalar wrAccesses;
+ Stats::Scalar rdMisses;
+ Stats::Scalar wrMisses;
+ } stats;
Fault translateInt(bool read, RequestPtr req, ThreadContext *tc);
@@ -149,11 +152,6 @@
TlbEntry *insert(Addr vpn, const TlbEntry &entry);
- /*
- * Function to register Stats
- */
- void regStats() override;
-
// Checkpointing
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32835
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a
Gerrit-Change-Number: 32835
Gerrit-PatchSet: 5
Gerrit-Owner: Emily Brickey <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Emily Brickey <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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