Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33356 )
Change subject: arch-arm: Rewrite addressTranslation to use BitUnions
......................................................................
arch-arm: Rewrite addressTranslation to use BitUnions
Change-Id: I48877d026213a0dec8b8f96deef59bdbc9a40564
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 1244d39..6ef9fe3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2345,7 +2345,7 @@
Fault fault = getDTBPtr(tc)->translateFunctional(
req, tc, mode, tran_type);
- RegVal newVal;
+ PAR par = 0;
if (fault == NoFault) {
Addr paddr = req->getPaddr();
uint64_t attr = getDTBPtr(tc)->getAttr();
@@ -2354,28 +2354,26 @@
attr |= 0x100;
attr &= ~ uint64_t(0x80);
}
- newVal = (paddr & mask(47, 12)) | attr;
+ par = (paddr & mask(47, 12)) | attr;
DPRINTF(MiscRegs,
"MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
- val, newVal);
+ val, par);
} else {
ArmFault *armFault = static_cast<ArmFault *>(fault.get());
armFault->update(tc);
// Set fault bit and FSR
FSR fsr = armFault->getFsr(tc);
- newVal = 1; // F bit
- newVal |= fsr << 1; // FST
- // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
- newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
- newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
- newVal |= 1 << 11; // RES1
+ par.f = 1; // F bit
+ par.fst = fsr.status; // FST
+ par.ptw = (armFault->iss() >> 7) & 0x1; // S1PTW
+ par.s = armFault->isStage2() ? 1 : 0; // S
DPRINTF(MiscRegs,
"MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
- val, fsr, newVal);
+ val, fsr, par);
}
- setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
+ setMiscRegNoEffect(MISCREG_PAR_EL1, par);
return;
}
@@ -2398,7 +2396,7 @@
Fault fault = getDTBPtr(tc)->translateFunctional(
req, tc, mode, tran_type);
- RegVal newVal;
+ PAR par = 0;
if (fault == NoFault) {
Addr paddr = req->getPaddr();
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
@@ -2413,36 +2411,36 @@
max_paddr_bit = 31;
}
- newVal = (paddr & mask(max_paddr_bit, 12)) |
+ par = (paddr & mask(max_paddr_bit, 12)) |
(getDTBPtr(tc)->getAttr());
DPRINTF(MiscRegs,
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
- val, newVal);
+ val, par);
} else {
ArmFault *armFault = static_cast<ArmFault *>(fault.get());
armFault->update(tc);
// Set fault bit and FSR
FSR fsr = armFault->getFsr(tc);
- newVal = ((fsr >> 9) & 1) << 11;
- if (newVal) {
+ par.f = 0x1; // F bit
+ par.lpae = fsr.lpae;
+ par.ptw = (armFault->iss() >> 7) & 0x1;
+ par.s = armFault->isStage2() ? 1 : 0;
+
+ if (par.lpae) {
// LPAE - rearange fault status
- newVal |= ((fsr >> 0) & 0x3f) << 1;
+ par.fst = fsr.status;
} else {
// VMSA - rearange fault status
- newVal |= ((fsr >> 0) & 0xf) << 1;
- newVal |= ((fsr >> 10) & 0x1) << 5;
- newVal |= ((fsr >> 12) & 0x1) << 6;
+ par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
+ par.fs5 = fsr.ext;
}
- newVal |= 0x1; // F bit
- newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
- newVal |= armFault->isStage2() ? 0x200 : 0;
DPRINTF(MiscRegs,
"MISCREG: Translated addr 0x%08x fault fsr %#x: PAR:
0x%08x\n",
- val, fsr, newVal);
+ val, fsr, par);
}
- setMiscRegNoEffect(MISCREG_PAR, newVal);
+ setMiscRegNoEffect(MISCREG_PAR, par);
return;
}
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index f6bfee4..7196496 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2019 ARM Limited
+ * Copyright (c) 2010-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -650,7 +650,12 @@
Bitfield<39, 12> pa;
Bitfield<11> lpae;
Bitfield<9> ns;
+ Bitfield<9> s;
Bitfield<8, 7> sh;
+ Bitfield<8> ptw;
+ Bitfield<6, 1> fst;
+ Bitfield<6> fs5;
+ Bitfield<5, 1> fs4_0;
Bitfield<0> f;
EndBitUnion(PAR)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33356
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I48877d026213a0dec8b8f96deef59bdbc9a40564
Gerrit-Change-Number: 33356
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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