Emily Brickey has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33394 )
Change subject: cpu-o3: convert lsq_unit to new style stats
......................................................................
cpu-o3: convert lsq_unit to new style stats
Removes unused stats: invAddrLoads, invAddrSwpfs, lsqBlockedLoads
Change-Id: Icd7fc6d8a040f4a1f9b190409b7cdb0a57fd68cf
---
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
4 files changed, 45 insertions(+), 87 deletions(-)
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 99dfd19..3465fbd 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -146,7 +146,6 @@
using namespace Stats;
instQueue.regStats();
- ldstQueue.regStats();
iewIdleCycles
.name(name() + ".iewIdleCycles")
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 1ca7d53..e536aad 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -117,16 +117,6 @@
template<class Impl>
void
-LSQ<Impl>::regStats()
-{
- //Initialize LSQs
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- thread[tid].regStats();
- }
-}
-
-template<class Impl>
-void
LSQ<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index e0cb68b..3a80aeb 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -45,6 +45,7 @@
#include <algorithm>
#include <cstring>
#include <map>
+#include <memory>
#include <queue>
#include "arch/generic/debugfaults.hh"
@@ -234,9 +235,6 @@
/** Returns the name of the LSQ unit. */
std::string name() const;
- /** Registers statistics. */
- void regStats();
-
/** Sets the pointer to the dcache port. */
void setDcachePort(MasterPort *dcache_port);
@@ -539,39 +537,37 @@
/** Flag for memory model. */
bool needsTSO;
+ protected:
// Will also need how many read/write ports the Dcache has. Or keep
track
// of that in stage that is one level up, and only call
executeLoad/Store
// the appropriate number of times.
- /** Total number of loads forwaded from LSQ stores. */
- Stats::Scalar lsqForwLoads;
+ struct LSQUnitStats : public Stats::Group{
+ LSQUnitStats(Stats::Group *parent);
- /** Total number of loads ignored due to invalid addresses. */
- Stats::Scalar invAddrLoads;
+ /** Total number of loads forwaded from LSQ stores. */
+ Stats::Scalar lsqForwLoads;
- /** Total number of squashed loads. */
- Stats::Scalar lsqSquashedLoads;
+ /** Total number of squashed loads. */
+ Stats::Scalar lsqSquashedLoads;
- /** Total number of responses from the memory system that are
- * ignored due to the instruction already being squashed. */
- Stats::Scalar lsqIgnoredResponses;
+ /** Total number of responses from the memory system that are
+ * ignored due to the instruction already being squashed. */
+ Stats::Scalar lsqIgnoredResponses;
- /** Tota number of memory ordering violations. */
- Stats::Scalar lsqMemOrderViolation;
+ /** Tota number of memory ordering violations. */
+ Stats::Scalar lsqMemOrderViolation;
- /** Total number of squashed stores. */
- Stats::Scalar lsqSquashedStores;
+ /** Total number of squashed stores. */
+ Stats::Scalar lsqSquashedStores;
- /** Total number of software prefetches ignored due to invalid
addresses. */
- Stats::Scalar invAddrSwpfs;
+ /** Number of loads that were rescheduled. */
+ Stats::Scalar lsqRescheduledLoads;
- /** Ready loads blocked due to partial store-forwarding. */
- Stats::Scalar lsqBlockedLoads;
+ /** Number of times the LSQ is blocked due to the cache. */
+ Stats::Scalar lsqCacheBlocked;
+ };
- /** Number of loads that were rescheduled. */
- Stats::Scalar lsqRescheduledLoads;
-
- /** Number of times the LSQ is blocked due to the cache. */
- Stats::Scalar lsqCacheBlocked;
+ std::unique_ptr<LSQUnitStats> stats;
public:
/** Executes the load at the given index. */
@@ -636,7 +632,7 @@
iewStage->rescheduleMemInst(load_inst);
load_inst->clearIssued();
load_inst->effAddrValid(false);
- ++lsqRescheduledLoads;
+ ++stats->lsqRescheduledLoads;
DPRINTF(LSQUnit, "Strictly ordered load [sn:%lli] PC %s\n",
load_inst->seqNum, load_inst->pcState());
@@ -790,7 +786,7 @@
cpu->schedule(wb, curTick());
// Don't need to do anything special for split loads.
- ++lsqForwLoads;
+ ++stats->lsqForwLoads;
return NoFault;
} else if (coverage ==
AddrRangeCoverage::PartialAddrRangeCoverage) {
@@ -817,7 +813,7 @@
iewStage->rescheduleMemInst(load_inst);
load_inst->clearIssued();
load_inst->effAddrValid(false);
- ++lsqRescheduledLoads;
+ ++stats->lsqRescheduledLoads;
// Do not generate a writeback event as this instruction
is not
// complete.
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 7383c6f..c29fb70 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -153,6 +153,8 @@
LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
LSQ *lsq_ptr, unsigned id)
{
+ stats = m5::make_unique<LSQUnitStats>(cpu_ptr);
+
lsqID = id;
cpu = cpu_ptr;
@@ -198,49 +200,20 @@
}
}
-template<class Impl>
-void
-LSQUnit<Impl>::regStats()
+template <class Impl>
+LSQUnit<Impl>::LSQUnitStats::LSQUnitStats(Stats::Group *parent)
+ : Stats::Group(parent, "LSQUnit"),
+ ADD_STAT(lsqForwLoads, "Number of loads that had data forwarded from"
+ " stores"),
+ ADD_STAT(lsqSquashedLoads, "Number of loads squashed"),
+ ADD_STAT(lsqIgnoredResponses, "Number of memory responses ignored"
+ " because the instruction is squashed"),
+ ADD_STAT(lsqMemOrderViolation, "Number of memory ordering
violations"),
+ ADD_STAT(lsqSquashedStores, "Number of stores squashed"),
+ ADD_STAT(lsqRescheduledLoads, "Number of loads that were
rescheduled"),
+ ADD_STAT(lsqCacheBlocked, "Number of times an access to memory
failed"
+ " due to the cache being blocked")
{
- lsqForwLoads
- .name(name() + ".forwLoads")
- .desc("Number of loads that had data forwarded from stores");
-
- invAddrLoads
- .name(name() + ".invAddrLoads")
- .desc("Number of loads ignored due to an invalid address");
-
- lsqSquashedLoads
- .name(name() + ".squashedLoads")
- .desc("Number of loads squashed");
-
- lsqIgnoredResponses
- .name(name() + ".ignoredResponses")
- .desc("Number of memory responses ignored because the instruction
is squashed");
-
- lsqMemOrderViolation
- .name(name() + ".memOrderViolation")
- .desc("Number of memory ordering violations");
-
- lsqSquashedStores
- .name(name() + ".squashedStores")
- .desc("Number of stores squashed");
-
- invAddrSwpfs
- .name(name() + ".invAddrSwpfs")
- .desc("Number of software prefetches ignored due to an invalid
address");
-
- lsqBlockedLoads
- .name(name() + ".blockedLoads")
- .desc("Number of blocked loads due to partial load-store
forwarding");
-
- lsqRescheduledLoads
- .name(name() + ".rescheduledLoads")
- .desc("Number of loads that were rescheduled");
-
- lsqCacheBlocked
- .name(name() + ".cacheBlocked")
- .desc("Number of times an access to memory failed due to the cache
being blocked");
}
template<class Impl>
@@ -481,7 +454,7 @@
inst->seqNum, ld_inst->seqNum,
ld_eff_addr1);
memDepViolator = ld_inst;
- ++lsqMemOrderViolation;
+ ++stats->lsqMemOrderViolation;
return std::make_shared<GenericISA::M5PanicFault>(
"Detected fault with inst [sn:%lli] and "
@@ -508,7 +481,7 @@
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
memDepViolator = ld_inst;
- ++lsqMemOrderViolation;
+ ++stats->lsqMemOrderViolation;
return std::make_shared<GenericISA::M5PanicFault>(
"Detected fault with "
@@ -883,7 +856,7 @@
--loads;
loadQueue.pop_back();
- ++lsqSquashedLoads;
+ ++stats->lsqSquashedLoads;
}
if (memDepViolator && squashed_num < memDepViolator->seqNum) {
@@ -921,7 +894,7 @@
--stores;
storeQueue.pop_back();
- ++lsqSquashedStores;
+ ++stats->lsqSquashedStores;
}
}
@@ -966,7 +939,7 @@
// Squashed instructions do not need to complete their access.
if (inst->isSquashed()) {
assert(!inst->isStore());
- ++lsqIgnoredResponses;
+ ++stats->lsqIgnoredResponses;
return;
}
@@ -1094,7 +1067,7 @@
} else {
if (cache_got_blocked) {
lsq->cacheBlocked(true);
- ++lsqCacheBlocked;
+ ++stats->lsqCacheBlocked;
}
if (!isLoad) {
assert(state->request() == storeWBIt->request());
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33394
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icd7fc6d8a040f4a1f9b190409b7cdb0a57fd68cf
Gerrit-Change-Number: 33394
Gerrit-PatchSet: 1
Gerrit-Owner: Emily Brickey <[email protected]>
Gerrit-MessageType: newchange
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