Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33198 )
Change subject: arm: Clear out isa_traits.hh.
......................................................................
arm: Clear out isa_traits.hh.
Remove unused constants, move the interrupt related constants to
arch/arm/interrupts.hh, move a paging related constant to
arch/arm/pagetable.hh, and get rid of unnecessary includes.
Change-Id: Ide219f7a8515e010c1dd029db2ef22d8f614d8a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33198
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/faults.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa_traits.hh
M src/arch/arm/pagetable.hh
M src/arch/arm/utility.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v3.hh
M src/dev/arm/vgic.cc
8 files changed, 25 insertions(+), 56 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 07d4ea8..5b865ec 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -42,6 +42,7 @@
#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/interrupts.hh"
#include "arch/arm/isa.hh"
#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
@@ -56,6 +57,8 @@
namespace ArmISA
{
+const uint32_t HighVecs = 0xFFFF0000;
+
uint8_t ArmFault::shortDescFaultSources[] = {
0x01, // AlignmentFault
0x04, // InstructionCacheMaintenance
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 695fd39..5c42dd9 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -54,6 +54,18 @@
namespace ArmISA
{
+enum InterruptTypes
+{
+ INT_RST,
+ INT_ABT,
+ INT_IRQ,
+ INT_FIQ,
+ INT_SEV, // Special interrupt for recieving SEV's
+ INT_VIRT_IRQ,
+ INT_VIRT_FIQ,
+ NumInterruptTypes
+};
+
class Interrupts : public BaseInterrupts
{
private:
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 2f8b634..4a7312c 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -42,67 +42,14 @@
#ifndef __ARCH_ARM_ISA_TRAITS_HH__
#define __ARCH_ARM_ISA_TRAITS_HH__
-#include "arch/arm/types.hh"
#include "base/types.hh"
-#include "cpu/static_inst_fwd.hh"
namespace ArmISA
{
const ByteOrder GuestByteOrder = LittleEndianByteOrder;
- StaticInstPtr decodeInst(ExtMachInst);
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
- const Addr Page_Mask = ~(PageBytes - 1);
- const Addr PageOffset = PageBytes - 1;
-
-
-
////////////////////////////////////////////////////////////////////////
- //
- // Translation stuff
- //
-
- const Addr PteShift = 3;
- const Addr NPtePageShift = PageShift - PteShift;
- const Addr NPtePage = ULL(1) << NPtePageShift;
- const Addr PteMask = NPtePage - 1;
-
- //// All 'Mapped' segments go through the TLB
- //// All other segments are translated by dropping the MSB, to give
- //// the corresponding physical address
- // User Segment - Mapped
- const Addr USegBase = ULL(0x0);
- const Addr USegEnd = ULL(0x7FFFFFFF);
-
- const unsigned VABits = 32;
- const unsigned PABits = 32; // Is this correct?
- const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
- const Addr VAddrUnImplMask = ~VAddrImplMask;
- inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
- inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
- inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
-
- const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
-
- // Max. physical address range in bits supported by the architecture
- const unsigned MaxPhysAddrRange = 48;
-
- const int MachineBytes = 4;
-
- const uint32_t HighVecs = 0xFFFF0000;
-
- enum InterruptTypes
- {
- INT_RST,
- INT_ABT,
- INT_IRQ,
- INT_FIQ,
- INT_SEV, // Special interrupt for recieving SEV's
- INT_VIRT_IRQ,
- INT_VIRT_FIQ,
- NumInterruptTypes
- };
} // namespace ArmISA
using namespace ArmISA;
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 054b6f5..9d1df1f 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -47,7 +47,11 @@
#include "arch/arm/utility.hh"
#include "sim/serialize.hh"
-namespace ArmISA {
+namespace ArmISA
+{
+
+// Max. physical address range in bits supported by the architecture
+const unsigned MaxPhysAddrRange = 48;
// ITB/DTB page table entry
struct PTE
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 1c44834..ad0a3da 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -40,6 +40,7 @@
#include <memory>
#include "arch/arm/faults.hh"
+#include "arch/arm/interrupts.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
@@ -74,8 +75,7 @@
}
} else {
if (size == (uint16_t)(-1))
- // todo: should this not be sizeof(uint32_t) rather?
- size = ArmISA::MachineBytes;
+ size = sizeof(uint32_t);
if (number < NumArgumentRegs) {
// If the argument is 64 bits, it must be in an even regiser
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 088d31e..d30a328 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -48,6 +48,7 @@
#include <vector>
+#include "arch/arm/interrupts.hh"
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "cpu/intr_control.hh"
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 1df0886..ecda6b6 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -41,6 +41,7 @@
#ifndef __DEV_ARM_GICV3_H__
#define __DEV_ARM_GICV3_H__
+#include "arch/arm/interrupts.hh"
#include "dev/arm/base_gic.hh"
#include "params/Gicv3.hh"
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 5ac597b..441e182 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -37,6 +37,7 @@
#include "dev/arm/vgic.hh"
+#include "arch/arm/interrupts.hh"
#include "base/trace.hh"
#include "debug/Checkpoint.hh"
#include "debug/VGIC.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ide219f7a8515e010c1dd029db2ef22d8f614d8a1
Gerrit-Change-Number: 33198
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Assignee: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Giacomo Gabrielli <[email protected]>
Gerrit-MessageType: merged
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