Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33504 )
Change subject: misc: Master/Slave terminology
......................................................................
misc: Master/Slave terminology
Changed CacheMasterPort and CacheSlavePort
Change-Id: I64b7449139544dd995e6f6960f1927caecc1e817
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 71eab09..be9b699 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -63,7 +63,7 @@
using namespace std;
-BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
+BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
: QueuedResponsePort(_name, _cache, queue),
@@ -129,7 +129,7 @@
}
void
-BaseCache::CacheSlavePort::setBlocked()
+BaseCache::CacheResponsePort::setBlocked()
{
assert(!blocked);
DPRINTF(CachePort, "Port is blocking new requests\n");
@@ -144,7 +144,7 @@
}
void
-BaseCache::CacheSlavePort::clearBlocked()
+BaseCache::CacheResponsePort::clearBlocked()
{
assert(blocked);
DPRINTF(CachePort, "Port is accepting new requests\n");
@@ -156,7 +156,7 @@
}
void
-BaseCache::CacheSlavePort::processSendRetry()
+BaseCache::CacheResponsePort::processSendRetry()
{
DPRINTF(CachePort, "Port is sending retry\n");
@@ -2364,7 +2364,7 @@
BaseCache::
CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
const std::string &_label)
- : CacheSlavePort(_name, _cache, _label), cache(_cache)
+ : CacheResponsePort(_name, _cache, _label), cache(_cache)
{
}
@@ -2451,7 +2451,7 @@
BaseCache::MemSidePort::MemSidePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
- : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
+ : CacheRequestPort(_name, _cache, _reqQueue, _snoopRespQueue),
_reqQueue(*_cache, *this, _snoopRespQueue, _label),
_snoopRespQueue(*_cache, *this, true, _label), cache(_cache)
{
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 176a7e5..80797d5 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -111,7 +111,7 @@
protected:
/**
- * A cache master port is used for the memory-side port of the
+ * A cache request port is used for the memory-side port of the
* cache, and in addition to the basic timing port that only sends
* response packets through a transmit list, it also offers the
* ability to schedule and send request packets (requests &
@@ -119,7 +119,7 @@
* and the sendDeferredPacket of the timing port is modified to
* consider both the transmit list and the requests from the MSHR.
*/
- class CacheMasterPort : public QueuedRequestPort
+ class CacheRequestPort : public QueuedRequestPort
{
public:
@@ -136,7 +136,7 @@
protected:
- CacheMasterPort(const std::string &_name, BaseCache *_cache,
+ CacheRequestPort(const std::string &_name, BaseCache *_cache,
ReqPacketQueue &_reqQueue,
SnoopRespPacketQueue &_snoopRespQueue) :
QueuedRequestPort(_name, _cache, _reqQueue, _snoopRespQueue)
@@ -202,10 +202,10 @@
/**
- * The memory-side port extends the base cache master port with
+ * The memory-side port extends the base cache request port with
* access functions for functional, atomic and timing snoops.
*/
- class MemSidePort : public CacheMasterPort
+ class MemSidePort : public CacheRequestPort
{
private:
@@ -234,14 +234,14 @@
};
/**
- * A cache slave port is used for the CPU-side port of the cache,
+ * A cache response port is used for the CPU-side port of the cache,
* and it is basically a simple timing port that uses a transmit
* list for responses to the CPU (or connected master). In
* addition, it has the functionality to block the port for
* incoming requests. If blocked, the port will issue a retry once
* unblocked.
*/
- class CacheSlavePort : public QueuedResponsePort
+ class CacheResponsePort : public QueuedResponsePort
{
public:
@@ -256,7 +256,7 @@
protected:
- CacheSlavePort(const std::string &_name, BaseCache *_cache,
+ CacheResponsePort(const std::string &_name, BaseCache *_cache,
const std::string &_label);
/** A normal packet queue used to store responses. */
@@ -275,10 +275,10 @@
};
/**
- * The CPU-side port extends the base cache slave port with access
+ * The CPU-side port extends the base cache response port with access
* functions for functional, atomic and timing requests.
*/
- class CpuSidePort : public CacheSlavePort
+ class CpuSidePort : public CacheResponsePort
{
private:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I64b7449139544dd995e6f6960f1927caecc1e817
Gerrit-Change-Number: 33504
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <eav...@ucdavis.edu>
Gerrit-MessageType: newchange
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