Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33507 )
Change subject: arch: MasterID to UniqueID
......................................................................
arch: MasterID to UniqueID
Change-Id: I14d4d4f09687fa8b883af243d7c4e7b15587527a
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/pagetable_walker.hh
8 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index 0980cc4..205a073 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -443,7 +443,7 @@
output_attributes = Param.String("ExtendedID[62:55]=MPAM_PMG, "
"ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS",
"User-defined transform to be applied to bus attributes like "
- "MasterID, ExtendedID or UserFlags. Currently, only works for "
+ "UniqueID, ExtendedID or UserFlags. Currently, only works for "
"MPAM Attributes encoding into bus attributes.")
has_DirtyVLPIOnLoad = Param.Bool(False, "GICR_VPENDBASER.Dirty
reflects "
"transient loading state when valid=1")
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 0ac7abe..2dfd3de 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -60,7 +60,7 @@
DmaPort port;
/** Request id for requests generated by this MMU */
- MasterID masterId;
+ UniqueID masterId;
public:
/** This translation class is used to trigger the data fetch once a
timing
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 1c89c22..3cbd301 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -97,7 +97,7 @@
}
void
-TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
+TableWalker::setMMU(Stage2MMU *m, UniqueID master_id)
{
stage2Mmu = m;
port = &m->getDMAPort();
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 6f04149..1597a65 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -829,8 +829,8 @@
/** Port shared by the two table walkers. */
DmaPort* port;
- /** Master id assigned by the MMU. */
- MasterID masterId;
+ /** Unique id assigned by the MMU. */
+ UniqueID masterId;
/** Indicates whether this table walker is part of the stage 2 mmu */
const bool isStage2;
@@ -912,7 +912,7 @@
void setTlb(TLB *_tlb) { tlb = _tlb; }
TLB* getTlb() { return tlb; }
- void setMMU(Stage2MMU *m, MasterID master_id);
+ void setMMU(Stage2MMU *m, UniqueID master_id);
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
uint8_t texcb, bool s);
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1d43a0d..0817b9b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -107,7 +107,7 @@
}
void
-TLB::setMMU(Stage2MMU *m, MasterID master_id)
+TLB::setMMU(Stage2MMU *m, UniqueID master_id)
{
stage2Mmu = m;
tableWalker->setMMU(m, master_id);
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 004ce0b..8bb3c9a 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -224,7 +224,7 @@
TableWalker *getTableWalker() { return tableWalker; }
- void setMMU(Stage2MMU *m, MasterID master_id);
+ void setMMU(Stage2MMU *m, UniqueID master_id);
int getsize() const { return size; }
diff --git a/src/arch/riscv/pagetable_walker.hh
b/src/arch/riscv/pagetable_walker.hh
index d9ab569..ccf7d1f 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -166,7 +166,7 @@
// The TLB we're supposed to load.
TLB * tlb;
System * sys;
- MasterID masterId;
+ UniqueID masterId;
// The number of outstanding walks that can be squashed per cycle.
unsigned numSquashable;
diff --git a/src/arch/x86/pagetable_walker.hh
b/src/arch/x86/pagetable_walker.hh
index 55bb098..96ce0e2 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -168,7 +168,7 @@
// The TLB we're supposed to load.
TLB * tlb;
System * sys;
- MasterID masterId;
+ UniqueID masterId;
// The number of outstanding walks that can be squashed per cycle.
unsigned numSquashable;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I14d4d4f09687fa8b883af243d7c4e7b15587527a
Gerrit-Change-Number: 33507
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <[email protected]>
Gerrit-MessageType: newchange
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