Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33520 )
Change subject: dev-arm: Update master/slave variables
......................................................................
dev-arm: Update master/slave variables
Change-Id: I2fa67b81f138b0b6691edc17d93f0585746ab343
---
M src/dev/arm/RealView.py
M src/dev/arm/UFSHostDevice.py
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 440292b..d157942 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -94,8 +94,8 @@
abstract = True
cxx_header = "dev/arm/amba_device.hh"
pio_addr = Param.Addr("Address for AMBA responder interface")
- pio_latency = Param.Latency("10ns",
- "Time between action and write/read result by AMBA DMA Device")
+ pio_latency = Param.Latency("10ns", "Time between action and
write/read"
+ "result by AMBA DMA Device")
interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
@@ -577,16 +577,16 @@
def _attach_memory(self, mem, bus, mem_ports=None):
if hasattr(mem, "port"):
if mem_ports is None:
- mem.port = bus.master
+ mem.port = bus.mem_side
else:
mem_ports.append(mem.port)
def _attach_device(self, device, bus, dma_ports=None):
if hasattr(device, "pio"):
- device.pio = bus.master
+ device.pio = bus.mem_side
if hasattr(device, "dma"):
if dma_ports is None:
- device.dma = bus.slave
+ device.dma = bus.cpu_side
else:
dma_ports.append(device.dma)
@@ -1093,15 +1093,15 @@
"""
Instantiate a single SMMU and attach a group of client devices to
it.
The devices' dma port is wired to the SMMU and the SMMU's dma port
- (master) is attached to the bus. In order to make it work, the list
+ (requestor) is attached to the bus. In order to make it work, the
list
of clients shouldn't contain any device part of the
_off_chip_devices
or _on_chip_devices.
This method should be called only once.
Parameters:
devices (list): List of devices which will be using the SMMU
- bus (Bus): The bus downstream of the SMMU. Its slave port will
- receive memory requests from the SMMU, and its
master
+ bus (Bus): The bus downstream of the SMMU. Its response port
will
+ receive memory requests from the SMMU, and its
request
port will forward accesses to the memory mapped
devices
"""
if hasattr(self, 'smmu'):
@@ -1109,8 +1109,8 @@
self.smmu = SMMUv3(reg_map=AddrRange(0x2b400000, size=0x00020000))
- self.smmu.master = bus.slave
- self.smmu.control = bus.master
+ self.smmu.mem_side = bus.cpu_side
+ self.smmu.control = bus.mem_side
dma_ports = []
for dev in devices:
diff --git a/src/dev/arm/UFSHostDevice.py b/src/dev/arm/UFSHostDevice.py
index a444a9a..879503a 100644
--- a/src/dev/arm/UFSHostDevice.py
+++ b/src/dev/arm/UFSHostDevice.py
@@ -42,7 +42,7 @@
class UFSHostDevice(DmaDevice):
type = 'UFSHostDevice'
cxx_header = "dev/arm/ufs_device.hh"
- pio_addr = Param.Addr("Address for SCSI configuration slave interface")
+ pio_addr = Param.Addr("Address for SCSI configuration responder
interface")
pio_latency = Param.Latency("10ns", "Time between action and
write/read \
result by AMBA DMA Device")
gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2fa67b81f138b0b6691edc17d93f0585746ab343
Gerrit-Change-Number: 33520
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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