Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33526 )
Change subject: arch-arm: Update instances of masterId
......................................................................
arch-arm: Update instances of masterId
smmu files
Change-Id: I0c1116ee954bd536b9beb7b832ce0e11ebc7eb77
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
6 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 745bb0f..1378cf9 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -49,13 +49,13 @@
Stage2MMU::Stage2MMU(const Params *p)
: SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
port(_stage1Tlb->getTableWalker(), p->sys),
- masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
+ _id(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
{
// we use the stage-one table walker as the parent of the port,
// and to get our master id, this is done to keep things
// symmetrical with other ISAs in terms of naming and stats
- stage1Tlb()->setMMU(this, masterId);
- stage2Tlb()->setMMU(this, masterId);
+ stage1Tlb()->setMMU(this, _id);
+ stage2Tlb()->setMMU(this, _id);
}
Fault
@@ -66,7 +66,7 @@
// translate to physical address using the second stage MMU
auto req = std::make_shared<Request>();
- req->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId,
0);
+ req->setVirt(descAddr, numBytes, flags | Request::PT_WALK, _id, 0);
if (isFunctional) {
fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
} else {
@@ -102,7 +102,7 @@
{
// translate to physical address using the second stage MMU
translation->setVirt(
- descAddr, numBytes, flags | Request::PT_WALK, masterId);
+ descAddr, numBytes, flags | Request::PT_WALK, _id);
translation->translateTiming(tc);
}
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 0ac7abe..ef6e7cb 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -60,7 +60,7 @@
DmaPort port;
/** Request id for requests generated by this MMU */
- MasterID masterId;
+ MasterID _id;
public:
/** This translation class is used to trigger the data fetch once a
timing
@@ -88,10 +88,10 @@
finish(const Fault &fault, const RequestPtr &req, ThreadContext
*tc,
BaseTLB::Mode mode);
- void setVirt(Addr vaddr, int size, Request::Flags flags, int
masterId)
+ void setVirt(Addr vaddr, int size, Request::Flags flags, int _id)
{
numBytes = size;
- req->setVirt(vaddr, size, flags, masterId, 0);
+ req->setVirt(vaddr, size, flags, _id, 0);
}
void translateTiming(ThreadContext *tc)
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 1c89c22..e9502f8 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -55,7 +55,7 @@
TableWalker::TableWalker(const Params *p)
: ClockedObject(p),
- stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
+ stage2Mmu(NULL), port(NULL), _id(Request::invldMasterId),
isStage2(p->is_stage2), tlb(NULL),
currState(NULL), pending(false),
numSquashable(p->num_squash_per_cycle),
@@ -97,11 +97,11 @@
}
void
-TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
+TableWalker::setMMU(Stage2MMU *m, MasterID unique_id)
{
stage2Mmu = m;
port = &m->getDMAPort();
- masterId = master_id;
+ _id = unique_id;
}
void
@@ -2122,7 +2122,7 @@
(this->*doDescriptor)();
} else {
RequestPtr req = std::make_shared<Request>(
- descAddr, numBytes, flags, masterId);
+ descAddr, numBytes, flags, _id);
req->taskId(ContextSwitchTaskId::DMA);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 6f04149..1d2b3f1 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -830,7 +830,7 @@
DmaPort* port;
/** Master id assigned by the MMU. */
- MasterID masterId;
+ MasterID _id;
/** Indicates whether this table walker is part of the stage 2 mmu */
const bool isStage2;
@@ -912,7 +912,7 @@
void setTlb(TLB *_tlb) { tlb = _tlb; }
TLB* getTlb() { return tlb; }
- void setMMU(Stage2MMU *m, MasterID master_id);
+ void setMMU(Stage2MMU *m, MasterID unique_id);
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
uint8_t texcb, bool s);
void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1d43a0d..f253dd9 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -107,10 +107,10 @@
}
void
-TLB::setMMU(Stage2MMU *m, MasterID master_id)
+TLB::setMMU(Stage2MMU *m, MasterID unique_id)
{
stage2Mmu = m;
- tableWalker->setMMU(m, master_id);
+ tableWalker->setMMU(m, unique_id);
}
bool
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 004ce0b..ae87676 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -224,7 +224,7 @@
TableWalker *getTableWalker() { return tableWalker; }
- void setMMU(Stage2MMU *m, MasterID master_id);
+ void setMMU(Stage2MMU *m, MasterID unique_id);
int getsize() const { return size; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c1116ee954bd536b9beb7b832ce0e11ebc7eb77
Gerrit-Change-Number: 33526
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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