Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33528 )
Change subject: cpu: Update instances of masterId
......................................................................
cpu: Update instances of masterId
Change-Id: Ied470bb9a08cb7676a2fce20d9c5349c2af8ade0
---
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/base_gen.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_gen.hh
M src/cpu/testers/traffic_gen/dram_rot_gen.hh
M src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/idle_gen.hh
M src/cpu/testers/traffic_gen/linear_gen.hh
M src/cpu/testers/traffic_gen/random_gen.hh
M src/cpu/testers/traffic_gen/trace_gen.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
27 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b016938..7fc18dd 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -58,7 +58,7 @@
void
CheckerCPU::init()
{
- masterId = systemPtr->getMasterId(this);
+ _id = systemPtr->getMasterId(this);
}
CheckerCPU::CheckerCPU(Params *p)
@@ -154,13 +154,13 @@
auto it_end = byte_enable.cbegin() + (size - size_left);
if (isAnyActiveElement(it_start, it_end)) {
mem_req = std::make_shared<Request>(frag_addr, frag_size,
- flags, masterId, thread->pcState().instAddr(),
+ flags, _id, thread->pcState().instAddr(),
tc->contextId());
mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
}
} else {
mem_req = std::make_shared<Request>(frag_addr, frag_size,
- flags, masterId, thread->pcState().instAddr(),
+ flags, _id, thread->pcState().instAddr(),
tc->contextId());
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3c04064..209dcfa 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -89,7 +89,7 @@
using VecRegContainer = TheISA::VecRegContainer;
/** id attached to all issued requests */
- MasterID masterId;
+ MasterID _id;
public:
void init() override;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 0656035..2b6058f 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -238,11 +238,11 @@
if (!curMacroStaticInst) {
// set up memory request for instruction fetch
auto mem_req = std::make_shared<Request>(
- fetch_PC, sizeof(MachInst), 0, masterId, fetch_PC,
+ fetch_PC, sizeof(MachInst), 0, _id, fetch_PC,
thread->contextId());
mem_req->setVirt(fetch_PC, sizeof(MachInst),
- Request::INST_FETCH, masterId,
+ Request::INST_FETCH, _id,
thread->instAddr());
fault = itb->translateFunctional(
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc
b/src/cpu/testers/directedtest/DirectedGenerator.cc
index 2d76b86..3502783 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -33,7 +33,7 @@
DirectedGenerator::DirectedGenerator(const Params *p)
: SimObject(p),
- masterId(p->system->getMasterId(this))
+ _id(p->system->getMasterId(this))
{
m_num_cpus = p->num_cpus;
m_directed_tester = NULL;
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh
b/src/cpu/testers/directedtest/DirectedGenerator.hh
index 2d03372..0f17ce1 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -49,7 +49,7 @@
protected:
int m_num_cpus;
- MasterID masterId;
+ MasterID _id;
RubyDirectedTester* m_directed_tester;
};
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc
b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index 5640163..9956e88 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -60,7 +60,7 @@
Packet::Command cmd;
// For simplicity, requests are assumed to be 1 byte-sized
- RequestPtr req = std::make_shared<Request>(m_address, 1, flags,
masterId);
+ RequestPtr req = std::make_shared<Request>(m_address, 1, flags, _id);
//
// Based on the current state, issue a load or a store
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 562b7d5..f17e632 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -60,7 +60,7 @@
Request::Flags flags;
// For simplicity, requests are assumed to be 1 byte-sized
- RequestPtr req = std::make_shared<Request>(m_address, 1, flags,
masterId);
+ RequestPtr req = std::make_shared<Request>(m_address, 1, flags, _id);
Packet::Command cmd;
bool do_write = (random_mt.random(0, 100) < m_percent_writes);
diff --git
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
index 87e940c..3266e93 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -90,7 +90,7 @@
injVnet(p->inj_vnet),
precision(p->precision),
responseLimit(p->response_limit),
- masterId(p->system->getMasterId(this))
+ _id(p->system->getMasterId(this))
{
// set up counters
noResponseCycles = 0;
@@ -290,18 +290,18 @@
if (injReqType == 0) {
// generate packet for virtual network 0
requestType = MemCmd::ReadReq;
- req = std::make_shared<Request>(paddr, access_size, flags,
masterId);
+ req = std::make_shared<Request>(paddr, access_size, flags, _id);
} else if (injReqType == 1) {
// generate packet for virtual network 1
requestType = MemCmd::ReadReq;
flags.set(Request::INST_FETCH);
req = std::make_shared<Request>(
- 0x0, access_size, flags, masterId, 0x0, 0);
+ 0x0, access_size, flags, _id, 0x0, 0);
req->setPaddr(paddr);
} else { // if (injReqType == 2)
// generate packet for virtual network 2
requestType = MemCmd::WriteReq;
- req = std::make_shared<Request>(paddr, access_size, flags,
masterId);
+ req = std::make_shared<Request>(paddr, access_size, flags, _id);
}
req->setContext(id);
diff --git
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
index 524a960..6a990bf 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -130,7 +130,7 @@
const Cycles responseLimit;
- MasterID masterId;
+ MasterID _id;
void completeRequest(PacketPtr pkt);
diff --git a/src/cpu/testers/memtest/memtest.cc
b/src/cpu/testers/memtest/memtest.cc
index 720b273..d408271 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -91,7 +91,7 @@
percentReads(p->percent_reads),
percentFunctional(p->percent_functional),
percentUncacheable(p->percent_uncacheable),
- masterId(p->system->getMasterId(this)),
+ _id(p->system->getMasterId(this)),
blockSize(p->system->cacheLineSize()),
blockAddrMask(blockSize - 1),
progressInterval(p->progress_interval),
@@ -241,7 +241,7 @@
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
- RequestPtr req = std::make_shared<Request>(paddr, 1, flags, masterId);
+ RequestPtr req = std::make_shared<Request>(paddr, 1, flags, _id);
req->setContext(id);
outstandingAddrs.insert(paddr);
diff --git a/src/cpu/testers/memtest/memtest.hh
b/src/cpu/testers/memtest/memtest.hh
index 86b27a4..432a51c 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -127,7 +127,7 @@
const unsigned percentUncacheable;
/** Request id for all generated traffic */
- MasterID masterId;
+ MasterID _id;
unsigned int id;
diff --git a/src/cpu/testers/rubytest/RubyTester.cc
b/src/cpu/testers/rubytest/RubyTester.cc
index 8dfe994..56cd5ad 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -53,7 +53,7 @@
: ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
false, Event::CPU_Tick_Pri),
- _masterId(p->system->getMasterId(this)),
+ _id(p->system->getMasterId(this)),
m_checkTable_ptr(nullptr),
m_num_cpus(p->num_cpus),
m_checks_to_complete(p->checks_to_complete),
diff --git a/src/cpu/testers/rubytest/RubyTester.hh
b/src/cpu/testers/rubytest/RubyTester.hh
index e63729a..e3a7fd6 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -117,11 +117,11 @@
void print(std::ostream& out) const;
bool getCheckFlush() { return m_check_flush; }
- MasterID masterId() { return _masterId; }
+ MasterID masterId() { return _id; }
protected:
EventFunctionWrapper checkStartEvent;
- MasterID _masterId;
+ MasterID _id;
private:
void hitCallback(NodeID proc, SubBlock* data);
diff --git a/src/cpu/testers/traffic_gen/base.cc
b/src/cpu/testers/traffic_gen/base.cc
index c1c0b46..421f1d5 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -78,7 +78,7 @@
retryPktTick(0), blockedWaitingResp(false),
updateEvent([this]{ update(); }, name()),
stats(this),
- masterID(system->getMasterId(this)),
+ _id(system->getMasterId(this)),
streamGenerator(StreamGen::create(p))
{
}
@@ -356,13 +356,13 @@
std::shared_ptr<BaseGen>
BaseTrafficGen::createIdle(Tick duration)
{
- return std::shared_ptr<BaseGen>(new IdleGen(*this, masterID,
duration));
+ return std::shared_ptr<BaseGen>(new IdleGen(*this, _id, duration));
}
std::shared_ptr<BaseGen>
BaseTrafficGen::createExit(Tick duration)
{
- return std::shared_ptr<BaseGen>(new ExitGen(*this, masterID,
duration));
+ return std::shared_ptr<BaseGen>(new ExitGen(*this, _id, duration));
}
std::shared_ptr<BaseGen>
@@ -371,7 +371,7 @@
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
{
- return std::shared_ptr<BaseGen>(new LinearGen(*this, masterID,
+ return std::shared_ptr<BaseGen>(new LinearGen(*this, _id,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
@@ -385,7 +385,7 @@
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
{
- return std::shared_ptr<BaseGen>(new RandomGen(*this, masterID,
+ return std::shared_ptr<BaseGen>(new RandomGen(*this, _id,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
@@ -404,7 +404,7 @@
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
{
- return std::shared_ptr<BaseGen>(new DramGen(*this, masterID,
+ return std::shared_ptr<BaseGen>(new DramGen(*this, _id,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
@@ -430,7 +430,7 @@
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
{
- return std::shared_ptr<BaseGen>(new DramRotGen(*this, masterID,
+ return std::shared_ptr<BaseGen>(new DramRotGen(*this, _id,
duration, start_addr,
end_addr, blocksize,
system->cacheLineSize(),
@@ -450,7 +450,7 @@
{
#if HAVE_PROTOBUF
return std::shared_ptr<BaseGen>(
- new TraceGen(*this, masterID, duration, trace_file, addr_offset));
+ new TraceGen(*this, _id, duration, trace_file, addr_offset));
#else
panic("Can't instantiate trace generation without Protobuf
support!\n");
#endif
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 2466206..8d25aec 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -301,7 +301,7 @@
/**
* MasterID used in generated requests.
*/
- const MasterID masterID;
+ const MasterID _id;
/** Currently active generator */
std::shared_ptr<BaseGen> activeGenerator;
diff --git a/src/cpu/testers/traffic_gen/base_gen.cc
b/src/cpu/testers/traffic_gen/base_gen.cc
index d5cdf71..e970dca 100644
--- a/src/cpu/testers/traffic_gen/base_gen.cc
+++ b/src/cpu/testers/traffic_gen/base_gen.cc
@@ -46,8 +46,8 @@
#include "debug/TrafficGen.hh"
#include "sim/system.hh"
-BaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration)
- : _name(obj.name()), masterID(master_id),
+BaseGen::BaseGen(SimObject &obj, MasterID unique_id, Tick _duration)
+ : _name(obj.name()), _id(unique_id),
duration(_duration)
{
}
@@ -57,10 +57,10 @@
Request::FlagsType flags)
{
// Create new request
- RequestPtr req = std::make_shared<Request>(addr, size, flags,
masterID);
+ RequestPtr req = std::make_shared<Request>(addr, size, flags, _id);
// Dummy PC to have PC-based prefetchers latch on; get entropy into
higher
// bits
- req->setPC(((Addr)masterID) << 2);
+ req->setPC(((Addr)_id) << 2);
// Embed it in a packet
PacketPtr pkt = new Packet(req, cmd);
@@ -69,19 +69,19 @@
pkt->dataDynamic(pkt_data);
if (cmd.isWrite()) {
- std::fill_n(pkt_data, req->getSize(), (uint8_t)masterID);
+ std::fill_n(pkt_data, req->getSize(), (uint8_t)_id);
}
return pkt;
}
StochasticGen::StochasticGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
- : BaseGen(obj, master_id, _duration),
+ : BaseGen(obj, unique_id, _duration),
startAddr(start_addr), endAddr(end_addr),
blocksize(_blocksize), cacheLineSize(cacheline_size),
minPeriod(min_period), maxPeriod(max_period),
diff --git a/src/cpu/testers/traffic_gen/base_gen.hh
b/src/cpu/testers/traffic_gen/base_gen.hh
index 0f51b6c..2a1f3f3 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -63,7 +63,7 @@
const std::string _name;
/** The MasterID used for generating requests */
- const MasterID masterID;
+ const MasterID _id;
/**
* Generate a new request and associated packet
@@ -85,10 +85,10 @@
* Create a base generator.
*
* @param obj simobject owning the generator
- * @param master_id MasterID set on each request
+ * @param unique_id MasterID set on each request
* @param _duration duration of this state before transitioning
*/
- BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
+ BaseGen(SimObject &obj, MasterID unique_id, Tick _duration);
virtual ~BaseGen() { }
@@ -133,7 +133,7 @@
{
public:
StochasticGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc
b/src/cpu/testers/traffic_gen/dram_gen.cc
index 0534a8a..fa32b5e 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_gen.cc
@@ -45,7 +45,7 @@
#include "enums/AddrMap.hh"
DramGen::DramGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
@@ -55,7 +55,7 @@
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
- : RandomGen(obj, master_id, _duration, start_addr, end_addr,
+ : RandomGen(obj, unique_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh
b/src/cpu/testers/traffic_gen/dram_gen.hh
index 081ca24..c6c3415 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_gen.hh
@@ -64,7 +64,7 @@
* Create a DRAM address sequence generator.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param unique_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -83,7 +83,7 @@
* assumes single channel system
*/
DramGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
index bb53d49..472ce93 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
@@ -63,7 +63,7 @@
* 3) Ranks per channel
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param unique_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -82,7 +82,7 @@
* @param addr_mapping Address mapping to be used,
* assumes single channel system
*/
- DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
+ DramRotGen(SimObject &obj, MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
@@ -92,7 +92,7 @@
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
- : DramGen(obj, master_id, _duration, start_addr, end_addr,
+ : DramGen(obj, unique_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit,
num_seq_pkts, page_size, nbr_of_banks_DRAM,
diff --git a/src/cpu/testers/traffic_gen/exit_gen.hh
b/src/cpu/testers/traffic_gen/exit_gen.hh
index ec863f7..3a5c7db 100644
--- a/src/cpu/testers/traffic_gen/exit_gen.hh
+++ b/src/cpu/testers/traffic_gen/exit_gen.hh
@@ -54,8 +54,8 @@
public:
- ExitGen(SimObject &obj, MasterID master_id, Tick _duration)
- : BaseGen(obj, master_id, _duration)
+ ExitGen(SimObject &obj, MasterID unique_id, Tick _duration)
+ : BaseGen(obj, unique_id, _duration)
{ }
void enter();
diff --git a/src/cpu/testers/traffic_gen/idle_gen.hh
b/src/cpu/testers/traffic_gen/idle_gen.hh
index 761b717..0311c1d 100644
--- a/src/cpu/testers/traffic_gen/idle_gen.hh
+++ b/src/cpu/testers/traffic_gen/idle_gen.hh
@@ -56,8 +56,8 @@
public:
- IdleGen(SimObject &obj, MasterID master_id, Tick _duration)
- : BaseGen(obj, master_id, _duration)
+ IdleGen(SimObject &obj, MasterID unique_id, Tick _duration)
+ : BaseGen(obj, unique_id, _duration)
{ }
void enter();
diff --git a/src/cpu/testers/traffic_gen/linear_gen.hh
b/src/cpu/testers/traffic_gen/linear_gen.hh
index b6f4282..005b8ad 100644
--- a/src/cpu/testers/traffic_gen/linear_gen.hh
+++ b/src/cpu/testers/traffic_gen/linear_gen.hh
@@ -67,7 +67,7 @@
* time.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param unique_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -79,12 +79,12 @@
* @param data_limit Upper limit on how much data to read/write
*/
LinearGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
- : StochasticGen(obj, master_id, _duration, start_addr, end_addr,
+ : StochasticGen(obj, unique_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
nextAddr(0),
diff --git a/src/cpu/testers/traffic_gen/random_gen.hh
b/src/cpu/testers/traffic_gen/random_gen.hh
index ba398a9..accbfe8 100644
--- a/src/cpu/testers/traffic_gen/random_gen.hh
+++ b/src/cpu/testers/traffic_gen/random_gen.hh
@@ -75,12 +75,12 @@
* @param data_limit Upper limit on how much data to read/write
*/
RandomGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ MasterID unique_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
- : StochasticGen(obj, master_id, _duration, start_addr, end_addr,
+ : StochasticGen(obj, unique_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
dataManipulated(0)
diff --git a/src/cpu/testers/traffic_gen/trace_gen.hh
b/src/cpu/testers/traffic_gen/trace_gen.hh
index fe386d8..15ee373 100644
--- a/src/cpu/testers/traffic_gen/trace_gen.hh
+++ b/src/cpu/testers/traffic_gen/trace_gen.hh
@@ -148,14 +148,14 @@
* Create a trace generator.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param unique_id MasterID related to the memory requests
* @param _duration duration of this state before transitioning
* @param trace_file File to read the transactions from
* @param addr_offset Positive offset to add to trace address
*/
- TraceGen(SimObject &obj, MasterID master_id, Tick _duration,
+ TraceGen(SimObject &obj, MasterID unique_id, Tick _duration,
const std::string& trace_file, Addr addr_offset)
- : BaseGen(obj, master_id, _duration),
+ : BaseGen(obj, unique_id, _duration),
trace(trace_file),
tickOffset(0),
addrOffset(addr_offset),
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 664b1fe..a21683f 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -650,7 +650,7 @@
// Create a request and the packet containing request
auto req = std::make_shared<Request>(
- node_ptr->physAddr, node_ptr->size, node_ptr->flags, masterID);
+ node_ptr->physAddr, node_ptr->size, node_ptr->flags, _id);
req->setReqInstSeqNum(node_ptr->seqNum);
req->setPC(node_ptr->pc);
@@ -658,7 +658,7 @@
// of the request.
if (node_ptr->virtAddr != 0) {
req->setVirt(node_ptr->virtAddr, node_ptr->size,
- node_ptr->flags, masterID, node_ptr->pc);
+ node_ptr->flags, _id, node_ptr->pc);
req->setPaddr(node_ptr->physAddr);
req->setReqInstSeqNum(node_ptr->seqNum);
}
@@ -1146,7 +1146,7 @@
{
// Create new request
- auto req = std::make_shared<Request>(addr, size, flags, masterID);
+ auto req = std::make_shared<Request>(addr, size, flags, _id);
req->setPC(pc);
// If this is not done it triggers assert in L1 cache for invalid
contextId
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 9ace810..ea046e2 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -423,11 +423,11 @@
public:
/* Constructor */
FixedRetryGen(TraceCPU& _owner, const std::string& _name,
- RequestPort& _port, MasterID master_id,
+ RequestPort& _port, MasterID unique_id,
const std::string& trace_file)
: owner(_owner),
port(_port),
- masterID(master_id),
+ _id(unique_id),
trace(trace_file),
genName(owner.name() + ".fixedretry" + _name),
retryPkt(nullptr),
@@ -504,7 +504,7 @@
RequestPort& port;
/** MasterID used for the requests being sent. */
- const MasterID masterID;
+ const MasterID _id;
/** Input stream used for reading the input trace file. */
InputStream trace;
@@ -847,11 +847,11 @@
public:
/* Constructor */
ElasticDataGen(TraceCPU& _owner, const std::string& _name,
- RequestPort& _port, MasterID master_id,
+ RequestPort& _port, MasterID unique_id,
const std::string& trace_file, TraceCPUParams *params)
: owner(_owner),
port(_port),
- masterID(master_id),
+ _id(unique_id),
trace(trace_file, 1.0 / params->freqMultiplier),
genName(owner.name() + ".elastic" + _name),
retryPkt(nullptr),
@@ -987,7 +987,7 @@
RequestPort& port;
/** MasterID used for the requests being sent. */
- const MasterID masterID;
+ const MasterID _id;
/** Input stream used for reading the input trace file. */
InputStream trace;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33528
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ied470bb9a08cb7676a2fce20d9c5349c2af8ade0
Gerrit-Change-Number: 33528
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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