[gem5-dev] Change in gem5/gem5[develop]: dev: replace master/slave in variables, params -mips

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33552 )

Change subject: dev: replace master/slave in variables, params -mips
......................................................................

dev: replace master/slave in variables, params -mips

Change-Id: I666f6d8feae88282510bf31232fd84fea13f055b
---
M src/dev/mips/Malta.py
M src/dev/sparc/T1000.py
2 files changed, 19 insertions(+), 19 deletions(-)



diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index baed7e8..6b9e85d 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -59,6 +59,6 @@
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.master
-        self.io.pio = bus.master
-        self.uart.pio = bus.master
+        self.cchip.pio = bus.mem_side
+        self.io.pio = bus.mem_side
+        self.uart.pio = bus.mem_side
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index dee2207..2b1bd16 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -112,8 +112,8 @@
     iob = Iob()
     # Attach I/O devices that are on chip
     def attachOnChipIO(self, bus):
-        self.iob.pio = bus.master
-        self.htod.pio = bus.master
+        self.iob.pio = bus.mem_side
+        self.htod.pio = bus.mem_side


     # Attach I/O devices to specified bus object.  Can't do this
@@ -122,17 +122,17 @@
     def attachIO(self, bus):
         self.hvuart.device = self.hterm
         self.puart0.device = self.pterm
-        self.fake_clk.pio = bus.master
-        self.fake_membnks.pio = bus.master
-        self.fake_l2_1.pio = bus.master
-        self.fake_l2_2.pio = bus.master
-        self.fake_l2_3.pio = bus.master
-        self.fake_l2_4.pio = bus.master
-        self.fake_l2esr_1.pio = bus.master
-        self.fake_l2esr_2.pio = bus.master
-        self.fake_l2esr_3.pio = bus.master
-        self.fake_l2esr_4.pio = bus.master
-        self.fake_ssi.pio = bus.master
-        self.fake_jbi.pio = bus.master
-        self.puart0.pio = bus.master
-        self.hvuart.pio = bus.master
+        self.fake_clk.pio = bus.mem_side
+        self.fake_membnks.pio = bus.mem_side
+        self.fake_l2_1.pio = bus.mem_side
+        self.fake_l2_2.pio = bus.mem_side
+        self.fake_l2_3.pio = bus.mem_side
+        self.fake_l2_4.pio = bus.mem_side
+        self.fake_l2esr_1.pio = bus.mem_side
+        self.fake_l2esr_2.pio = bus.mem_side
+        self.fake_l2esr_3.pio = bus.mem_side
+        self.fake_l2esr_4.pio = bus.mem_side
+        self.fake_ssi.pio = bus.mem_side
+        self.fake_jbi.pio = bus.mem_side
+        self.puart0.pio = bus.mem_side
+        self.hvuart.pio = bus.mem_side

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I666f6d8feae88282510bf31232fd84fea13f055b
Gerrit-Change-Number: 33552
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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