Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33637 )
Change subject: mem-cache,mem-ruby: Update getMasterId()
......................................................................
mem-cache,mem-ruby: Update getMasterId()
Change-Id: I3162ae95ba4364d4c87f3a0ffcf898f627dbaf6f
---
M src/arch/arm/stage2_mmu.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/pagetable_walker.hh
M src/cpu/base.cc
M src/cpu/checker/cpu.cc
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/trace/trace_cpu.cc
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/smmu_v3.cc
M src/dev/dma_device.cc
M src/gpu-compute/compute_unit.cc
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/external_master.cc
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/RubySystem.cc
M src/sim/system.cc
M src/sim/system.hh
24 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 745bb0f..dcebdc4 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -49,7 +49,7 @@
Stage2MMU::Stage2MMU(const Params *p)
: SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
port(_stage1Tlb->getTableWalker(), p->sys),
- masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
+ masterId(p->sys->getUniqueId(_stage1Tlb->getTableWalker()))
{
// we use the stage-one table walker as the parent of the port,
// and to get our master id, this is done to keep things
diff --git a/src/arch/riscv/pagetable_walker.hh
b/src/arch/riscv/pagetable_walker.hh
index d9ab569..6e329c7 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -202,7 +202,7 @@
Walker(const Params *params) :
ClockedObject(params), port(name() + ".port", this),
funcState(this, NULL, NULL, true), tlb(NULL),
sys(params->system),
- masterId(sys->getMasterId(this)),
+ masterId(sys->getUniqueId(this)),
numSquashable(params->num_squash_per_cycle),
startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
{
diff --git a/src/arch/x86/pagetable_walker.hh
b/src/arch/x86/pagetable_walker.hh
index 55bb098..0f8472c 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -204,7 +204,7 @@
Walker(const Params *params) :
ClockedObject(params), port(name() + ".port", this),
funcState(this, NULL, NULL, true), tlb(NULL),
sys(params->system),
- masterId(sys->getMasterId(this)),
+ masterId(sys->getUniqueId(this)),
numSquashable(params->num_squash_per_cycle),
startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
{
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index fb99712..0ae6ae5 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -122,8 +122,8 @@
BaseCPU::BaseCPU(Params *p, bool is_checker)
: ClockedObject(p), instCnt(0), _cpuId(p->cpu_id),
_socketId(p->socket_id),
- _instMasterId(p->system->getMasterId(this, "inst")),
- _dataMasterId(p->system->getMasterId(this, "data")),
+ _instMasterId(p->system->getUniqueId(this, "inst")),
+ _dataMasterId(p->system->getUniqueId(this, "data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
_switchedOut(p->switched_out),
_cacheLineSize(p->system->cacheLineSize()),
interrupts(p->interrupts), numThreads(p->numThreads),
system(p->system),
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b016938..5d05c3f 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -58,7 +58,7 @@
void
CheckerCPU::init()
{
- masterId = systemPtr->getMasterId(this);
+ masterId = systemPtr->getUniqueId(this);
}
CheckerCPU::CheckerCPU(Params *p)
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc
b/src/cpu/testers/directedtest/DirectedGenerator.cc
index 2d76b86..c710858 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -33,7 +33,7 @@
DirectedGenerator::DirectedGenerator(const Params *p)
: SimObject(p),
- masterId(p->system->getMasterId(this))
+ masterId(p->system->getUniqueId(this))
{
m_num_cpus = p->num_cpus;
m_directed_tester = NULL;
diff --git
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
index 87e940c..ecad2b6 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -90,7 +90,7 @@
injVnet(p->inj_vnet),
precision(p->precision),
responseLimit(p->response_limit),
- masterId(p->system->getMasterId(this))
+ masterId(p->system->getUniqueId(this))
{
// set up counters
noResponseCycles = 0;
diff --git a/src/cpu/testers/memtest/memtest.cc
b/src/cpu/testers/memtest/memtest.cc
index 720b273..26ccd23 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -91,7 +91,7 @@
percentReads(p->percent_reads),
percentFunctional(p->percent_functional),
percentUncacheable(p->percent_uncacheable),
- masterId(p->system->getMasterId(this)),
+ masterId(p->system->getUniqueId(this)),
blockSize(p->system->cacheLineSize()),
blockAddrMask(blockSize - 1),
progressInterval(p->progress_interval),
diff --git a/src/cpu/testers/rubytest/RubyTester.cc
b/src/cpu/testers/rubytest/RubyTester.cc
index 8dfe994..76fe8f0 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -53,7 +53,7 @@
: ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
false, Event::CPU_Tick_Pri),
- _masterId(p->system->getMasterId(this)),
+ _masterId(p->system->getUniqueId(this)),
m_checkTable_ptr(nullptr),
m_num_cpus(p->num_cpus),
m_checks_to_complete(p->checks_to_complete),
diff --git a/src/cpu/testers/traffic_gen/base.cc
b/src/cpu/testers/traffic_gen/base.cc
index c1c0b46..96faa10 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -78,7 +78,7 @@
retryPktTick(0), blockedWaitingResp(false),
updateEvent([this]{ update(); }, name()),
stats(this),
- masterID(system->getMasterId(this)),
+ masterID(system->getUniqueId(this)),
streamGenerator(StreamGen::create(p))
{
}
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index dd91257..2962287 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -46,8 +46,8 @@
: BaseCPU(params),
icachePort(this),
dcachePort(this),
- instMasterID(params->system->getMasterId(this, "inst")),
- dataMasterID(params->system->getMasterId(this, "data")),
+ instMasterID(params->system->getUniqueId(this, "inst")),
+ dataMasterID(params->system->getUniqueId(this, "data")),
instTraceFile(params->instTraceFile),
dataTraceFile(params->dataTraceFile),
icacheGen(*this, ".iside", icachePort, instMasterID,
instTraceFile),
diff --git a/src/dev/arm/gic_v3_its.cc b/src/dev/arm/gic_v3_its.cc
index 442008f..7319b30 100644
--- a/src/dev/arm/gic_v3_its.cc
+++ b/src/dev/arm/gic_v3_its.cc
@@ -779,7 +779,7 @@
gitsCbaser(0), gitsCreadr(0),
gitsCwriter(0), gitsIidr(0),
tableBases(NUM_BASER_REGS, 0),
- masterId(params->system->getMasterId(this)),
+ masterId(params->system->getUniqueId(this)),
gic(nullptr),
commandEvent([this] { checkCommandQueue(); }, name()),
pendingCommands(false),
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index f9d99da..004cb68 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -54,7 +54,7 @@
SMMUv3::SMMUv3(SMMUv3Params *params) :
ClockedObject(params),
system(*params->system),
- masterId(params->system->getMasterId(this)),
+ masterId(params->system->getUniqueId(this)),
masterPort(name() + ".master", *this),
masterTableWalkPort(name() + ".master_walker", *this),
controlPort(name() + ".control", *this, params->reg_map),
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 03882e3..fafd726 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -52,7 +52,7 @@
DmaPort::DmaPort(ClockedObject *dev, System *s,
uint32_t sid, uint32_t ssid)
: RequestPort(dev->name() + ".dma", dev),
- device(dev), sys(s), masterId(s->getMasterId(dev)),
+ device(dev), sys(s), masterId(s->getUniqueId(dev)),
sendEvent([this]{ sendDma(); }, dev->name()),
pendingCount(0), inRetry(false),
defaultSid(sid),
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index 075e926..d1e520a 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -94,7 +94,7 @@
countPages(p->countPages),
req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
- _masterId(p->system->getMasterId(this, "ComputeUnit")),
+ _masterId(p->system->getUniqueId(this, "ComputeUnit")),
lds(*p->localDataStore), gmTokenPort(name() + ".gmTokenPort", this),
_cacheLineSize(p->system->cacheLineSize()),
_numBarrierSlots(p->num_barrier_slots),
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index d52f7fd..d1f87cd 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -92,7 +92,7 @@
: ClockedObject(p), listeners(), cache(nullptr),
blkSize(p->block_size),
lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
- masterId(p->sys->getMasterId(this)),
pageBytes(p->sys->getPageBytes()),
+ masterId(p->sys->getUniqueId(this)),
pageBytes(p->sys->getPageBytes()),
prefetchOnAccess(p->prefetch_on_access),
useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
usefulPrefetches(0), tlb(nullptr)
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 7009db7..f39bad2 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -152,7 +152,7 @@
* Gets the requestor ID that generated this address
* @return the requestor ID that generated this address
*/
- MasterID getMasterId() const
+ MasterID getUniqueId() const
{
return masterId;
}
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index 36773c6..1f1a32e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -124,7 +124,7 @@
Addr pf_addr = pfi.getAddr();
Addr pc = pfi.getPC();
bool is_secure = pfi.isSecure();
- MasterID master_id = useMasterId ? pfi.getMasterId() : 0;
+ MasterID master_id = useMasterId ? pfi.getUniqueId() : 0;
// Get corresponding pc table
PCTable* pcTable = findTable(master_id);
diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 1a1ec40..1093f60 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -53,7 +53,7 @@
portName(params->name + ".port"),
portType(params->port_type),
portData(params->port_data),
- masterId(params->system->getMasterId(this))
+ masterId(params->system->getUniqueId(this))
{}
Port &
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index dd3a9e7..7309982 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -50,7 +50,7 @@
AbstractController::AbstractController(const Params *p)
: ClockedObject(p), Consumer(this), m_version(p->version),
m_clusterID(p->cluster_id),
- m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
+ m_masterId(p->system->getUniqueId(this)), m_is_blocking(false),
m_number_of_TBEs(p->number_of_TBEs),
m_transitions_per_cycle(p->transitions_per_cycle),
m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index daa52da..adc2bc1 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -147,7 +147,7 @@
public:
MachineID getMachineID() const { return m_machineID; }
- MasterID getMasterId() const { return m_masterId; }
+ MasterID getUniqueId() const { return m_masterId; }
Stats::Histogram& getDelayHist() { return m_delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
diff --git a/src/mem/ruby/system/RubySystem.cc
b/src/mem/ruby/system/RubySystem.cc
index f07682b..48104a9 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -139,7 +139,7 @@
// the system's list of MasterIDs and add missing MasterIDs to network
0
// (the default).
for (auto& cntrl : m_abs_cntrl_vec) {
- MasterID mid = cntrl->getMasterId();
+ MasterID mid = cntrl->getUniqueId();
MachineID mach_id = cntrl->getMachineID();
// These are setup in Network constructor and should exist
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 07dae86..621c48d 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -248,11 +248,11 @@
// Get the generic system master IDs
MasterID tmp_id M5_VAR_USED;
- tmp_id = getMasterId(this, "writebacks");
+ tmp_id = getUniqueId(this, "writebacks");
assert(tmp_id == Request::wbMasterId);
- tmp_id = getMasterId(this, "functional");
+ tmp_id = getUniqueId(this, "functional");
assert(tmp_id == Request::funcMasterId);
- tmp_id = getMasterId(this, "interrupt");
+ tmp_id = getUniqueId(this, "interrupt");
assert(tmp_id == Request::intMasterId);
// increment the number of running systems
@@ -593,18 +593,18 @@
MasterID
System::getGlobalMasterId(const std::string& master_name)
{
- return _getMasterId(nullptr, master_name);
+ return _getUniqueId(nullptr, master_name);
}
MasterID
-System::getMasterId(const SimObject* master, std::string submaster)
+System::getUniqueId(const SimObject* master, std::string submaster)
{
auto master_name = leafMasterName(master, submaster);
- return _getMasterId(master, master_name);
+ return _getUniqueId(master, master_name);
}
MasterID
-System::_getMasterId(const SimObject* master, const std::string&
master_name)
+System::_getUniqueId(const SimObject* master, const std::string&
master_name)
{
std::string name = stripSystemName(master_name);
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 22318f7..4374e02 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -460,8 +460,8 @@
* For a cpu having two masters: a data master and an instruction
master,
* the method must be called twice:
*
- * instMasterId = getMasterId(cpu, "inst");
- * dataMasterId = getMasterId(cpu, "data");
+ * instMasterId = getUniqueId(cpu, "inst");
+ * dataMasterId = getUniqueId(cpu, "data");
*
* and the masters' names will be:
* - "cpu.inst"
@@ -471,7 +471,7 @@
* @param submaster String containing the submaster's name
* @return the master's ID.
*/
- MasterID getMasterId(const SimObject* master,
+ MasterID getUniqueId(const SimObject* master,
std::string submaster = std::string());
/**
@@ -505,8 +505,8 @@
MasterID maxMasters() { return masters.size(); }
protected:
- /** helper function for getMasterId */
- MasterID _getMasterId(const SimObject* master,
+ /** helper function for getUniqueId */
+ MasterID _getUniqueId(const SimObject* master,
const std::string& master_name);
/**
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33637
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3162ae95ba4364d4c87f3a0ffcf898f627dbaf6f
Gerrit-Change-Number: 33637
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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