Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )
Change subject: sim: Expose the system's byte order as a param
......................................................................
sim: Expose the system's byte order as a param
There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.
Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro <[email protected]>
Reviewed-by: Gabe Black <[email protected]>
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/System.py b/src/sim/System.py
index dcef74b..caf32fb 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -48,6 +48,11 @@
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
'atomic_noncaching']
+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+ default_byte_order = 'big'
+else:
+ default_byte_order = 'little'
+
class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
@@ -84,6 +89,9 @@
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
+ byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
exit_on_work_items = Param.Bool(False, "Exit from the simulation loop
when "
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8e2c472..8b31b2f 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
ByteOrder
getGuestByteOrder() const
{
-#if THE_ISA != NULL_ISA
- return TheISA::GuestByteOrder;
-#else
- panic("The NULL ISA has no endianness.");
-#endif
+ return _params->byte_order;
}
/**
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Gerrit-Change-Number: 33175
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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