Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )
Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
......................................................................
base, sim, mem, arch: Remove the dummy CPU in NULL
The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.
Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg <[email protected]>
---
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
9 files changed, 9 insertions(+), 100 deletions(-)
diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-if env['TARGET_ISA'] == 'null':
- Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..0000000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..0000000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_NULL_CPU_DUMMY_HH__
-#define __ARCH_NULL_CPU_DUMMY_HH__
-
-#include "sim/core.hh"
-
-class BaseCPU
-{
- public:
- static int numSimulatedInsts() { return 0; }
- static int numSimulatedOps() { return 0; }
- static void wakeup(ThreadID tid) { ; }
-};
-
-#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 3ef5519..82bec20 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -48,7 +48,7 @@
// and if so stop here
#include "config/the_isa.hh"
#if THE_ISA == NULL_ISA
-#include "arch/null/cpu_dummy.hh"
+#error Including BaseCPU in a system without CPU support
#else
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index f1e9dba..b53e231 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -45,7 +45,6 @@
#include "arch/locked_mem.hh"
#include "base/loader/memory_image.hh"
#include "base/loader/object_file.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 4e484e5..68cc1ed 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -48,7 +48,6 @@
#include <cassert>
#include "base/intmath.hh"
-#include "cpu/base.hh"
#include "mem/cache/base.hh"
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 9464c0d..0f5ae7e 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -53,7 +53,10 @@
#include "base/hostinfo.hh"
#include "base/statistics.hh"
#include "base/time.hh"
+#include "config/the_isa.hh"
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "sim/global_event.hh"
using namespace std;
@@ -108,6 +111,7 @@
Global::Global()
{
+#if THE_ISA != NULL_ISA
simInsts
.functor(BaseCPU::numSimulatedInsts)
.name("sim_insts")
@@ -123,6 +127,7 @@
.precision(0)
.prereq(simOps)
;
+#endif
simSeconds
.name("sim_seconds")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 8185f13..da454b0 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -50,12 +50,15 @@
#include "base/loader/symtab.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "config/use_kvm.hh"
#if USE_KVM
#include "cpu/kvm/base.hh"
#include "cpu/kvm/vm.hh"
#endif
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/Quiesce.hh"
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8b31b2f..5e7e688 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -52,7 +52,6 @@
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_master.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Gerrit-Change-Number: 34236
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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