Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/34335 )

Change subject: arch-arm: Initialize some cases of destReg
......................................................................

arch-arm: Initialize some cases of destReg

Some compilers complained that this variable may be uninitialized. This
change initializes it to 0.

Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Signed-off-by: Jason Lowe-Power <[email protected]>
---
M src/arch/arm/isa/insts/neon.isa
M src/arch/arm/isa/insts/neon64.isa
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 1dfefe7..c8f8fcd 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1452,7 +1452,7 @@
         rCount = 2
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1, srcReg2;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         for reg in range(rCount):
             eWalkCode += '''
@@ -1654,7 +1654,7 @@
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         for reg in range(2):
             eWalkCode += '''
@@ -1884,7 +1884,7 @@
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcRegs;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         for reg in range(rCount):
             eWalkCode += '''
@@ -2010,7 +2010,7 @@
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         for reg in range(2):
             eWalkCode += '''
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index b9729a1..702c128 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -351,7 +351,7 @@
         global header_output, exec_output
         eWalkCode = simd64EnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         destReg = 0 if not hi else 2
         for reg in range(2):
@@ -632,7 +632,7 @@
         global header_output, exec_output
         eWalkCode = simd64EnabledCheckCode + '''
         RegVect srcRegs;
-        BigRegVect destReg;
+        BigRegVect destReg = {0};
         '''
         for reg in range(rCount):
             eWalkCode += '''

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Gerrit-Change-Number: 34335
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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