Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34418 )
Change subject: arch-arm: Fix ArmISA namespace requirement for Arm KVM
......................................................................
arch-arm: Fix ArmISA namespace requirement for Arm KVM
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34418
Reviewed-by: Gabe Black <gabebl...@google.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/kvm/arm_cpu.hh
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/kvm/base_cpu.cc
4 files changed, 12 insertions(+), 8 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh
index 28453d7..cc3c935 100644
--- a/src/arch/arm/kvm/arm_cpu.hh
+++ b/src/arch/arm/kvm/arm_cpu.hh
@@ -71,7 +71,7 @@
/** KVM ID */
const uint64_t id;
/** gem5 index */
- const IntRegIndex idx;
+ const ArmISA::IntRegIndex idx;
/** Name in debug output */
const char *name;
};
@@ -80,7 +80,7 @@
/** KVM ID */
const uint64_t id;
/** gem5 index */
- const MiscRegIndex idx;
+ const ArmISA::MiscRegIndex idx;
/** Name in debug output */
const char *name;
};
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index b8ada8d..1001f81 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -42,6 +42,8 @@
#include "debug/KvmContext.hh"
#include "params/ArmV8KvmCPU.hh"
+using namespace ArmISA;
+
// Unlike gem5, kvm doesn't count the SP as a normal integer register,
// which means we only have 31 normal integer registers.
constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1;
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 9870510..dae9fe7 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -93,27 +93,27 @@
protected:
/** Mapping between integer registers in gem5 and KVM */
struct IntRegInfo {
- IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name)
+ IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char
*_name)
: kvm(_kvm), idx(_idx), name(_name) {}
/** Register index in KVM */
uint64_t kvm;
/** Register index in gem5 */
- IntRegIndex idx;
+ ArmISA::IntRegIndex idx;
/** Name to use in debug dumps */
const char *name;
};
/** Mapping between misc registers in gem5 and registers in KVM */
struct MiscRegInfo {
- MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name,
- bool _is_device = false)
+ MiscRegInfo(uint64_t _kvm, ArmISA::MiscRegIndex _idx,
+ const char *_name, bool _is_device = false)
: kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {}
/** Register index in KVM */
uint64_t kvm;
/** Register index in gem5 */
- MiscRegIndex idx;
+ ArmISA::MiscRegIndex idx;
/** Name to use in debug dumps */
const char *name;
/** is device register? (needs 'effectful' state update) */
@@ -137,7 +137,7 @@
/** Mapping between gem5 misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap;
/** Device registers (needing "effectful" MiscReg writes) */
- static const std::set<MiscRegIndex> deviceRegSet;
+ static const std::set<ArmISA::MiscRegIndex> deviceRegSet;
/** Mapping between gem5 ID misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap;
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 04c5d0f..6fd2651 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -45,6 +45,8 @@
#include "params/BaseArmKvmCPU.hh"
#include "params/GenericTimer.hh"
+using namespace ArmISA;
+
#define INTERRUPT_ID(type, vcpu, irq) ( \
((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34418
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9
Gerrit-Change-Number: 34418
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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