Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34980 )
Change subject: arch-riscv: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-riscv: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
4 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b39005f..5ef68fe 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1848,8 +1848,7 @@
"sfence in user mode or TVM
enabled",
machInst);
}
- xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
- xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+ xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
0x18: mret({{
if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 7da666d..145d82e 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -155,15 +155,15 @@
{
if (FullSystem)
{
- TLB *tlb = dynamic_cast<TLB *>(context()->getDTBPtr());
+ MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
unsigned logBytes;
Addr paddr = va;
- PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+ PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
SATP satp = context()->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
- Walker *walker = tlb->getWalker();
+ Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index caa2a7a..221110b 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -411,13 +411,13 @@
Addr paddr = vaddr;
if (FullSystem) {
- TLB *tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
+ MMU *mmu = static_cast<MMU *>(tc->getMMUPtr());
- PrivilegeMode pmode = tlb->getMemPriv(tc, mode);
+ PrivilegeMode pmode = mmu->getMemPriv(tc, mode);
SATP satp = tc->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
- Walker *walker = tlb->getWalker();
+ Walker *walker = mmu->getDataWalker();
unsigned logBytes;
Fault fault = walker->startFunctional(
tc, paddr, logBytes, mode);
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 9604b53..c9fe986 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -133,6 +133,18 @@
{
public:
MMU(const RiscvMMUParams *p);
+
+ PrivilegeMode
+ getMemPriv(ThreadContext *tc, BaseTLB::Mode mode)
+ {
+ return static_cast<TLB*>(dtb)->getMemPriv(tc, mode);
+ }
+
+ Walker *
+ getDataWalker()
+ {
+ return static_cast<TLB*>(dtb)->getWalker();
+ }
};
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34980
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Gerrit-Change-Number: 34980
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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