Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35238 )
Change subject: arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D
flavours
......................................................................
arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D flavours
This will be exploited by the incoming patchset
Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/tlbi_op.hh
1 file changed, 12 insertions(+), 26 deletions(-)
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 8706d3d..4c41068 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019 ARM Limited
+ * Copyright (c) 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -89,11 +89,11 @@
};
/** Instruction TLB Invalidate All */
-class ITLBIALL : public TLBIOp
+class ITLBIALL : public TLBIALL
{
public:
ITLBIALL(ExceptionLevel _targetEL, bool _secure)
- : TLBIOp(_targetEL, _secure)
+ : TLBIALL(_targetEL, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -102,11 +102,11 @@
};
/** Data TLB Invalidate All */
-class DTLBIALL : public TLBIOp
+class DTLBIALL : public TLBIALL
{
public:
DTLBIALL(ExceptionLevel _targetEL, bool _secure)
- : TLBIOp(_targetEL, _secure)
+ : TLBIALL(_targetEL, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -129,19 +129,16 @@
};
/** Instruction TLB Invalidate by ASID match */
-class ITLBIASID : public TLBIOp
+class ITLBIASID : public TLBIASID
{
public:
ITLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
- : TLBIOp(_targetEL, _secure), asid(_asid)
+ : TLBIASID(_targetEL, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
-
- protected:
- uint16_t asid;
};
/** Data TLB Invalidate by ASID match */
@@ -149,15 +146,12 @@
{
public:
DTLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
- : TLBIOp(_targetEL, _secure), asid(_asid)
+ : TLBIASID(_targetEL, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
-
- protected:
- uint16_t asid;
};
/** TLB Invalidate All, Non-Secure */
@@ -203,39 +197,31 @@
};
/** Instruction TLB Invalidate by VA */
-class ITLBIMVA : public TLBIOp
+class ITLBIMVA : public TLBIMVA
{
public:
ITLBIMVA(ExceptionLevel _targetEL, bool _secure,
Addr _addr, uint16_t _asid)
- : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
+ : TLBIMVA(_targetEL, _secure, _addr, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
-
- protected:
- Addr addr;
- uint16_t asid;
};
/** Data TLB Invalidate by VA */
-class DTLBIMVA : public TLBIOp
+class DTLBIMVA : public TLBIMVA
{
public:
DTLBIMVA(ExceptionLevel _targetEL, bool _secure,
Addr _addr, uint16_t _asid)
- : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
+ : TLBIMVA(_targetEL, _secure, _addr, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
-
- protected:
- Addr addr;
- uint16_t asid;
};
/** TLB Invalidate by Intermediate Physical Address */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Gerrit-Change-Number: 35238
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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