Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35239 )

Change subject: arch-arm: Reimplement TLB::flushAll
......................................................................

arch-arm: Reimplement TLB::flushAll

flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
2 files changed, 30 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a0f837d..8cb7638 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016-2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -245,6 +245,29 @@
 }

 void
+TLB::flushAll()
+{
+    DPRINTF(TLB, "Flushing all TLB entries\n");
+    int x = 0;
+    TlbEntry *te;
+    while (x < size) {
+        te = &table[x];
+
+        DPRINTF(TLB, " -  %s\n", te->print());
+        te->valid = false;
+        stats.flushedEntries++;
+        ++x;
+    }
+
+    stats.flushTlb++;
+
+ // If there's a second stage TLB (and we're not it) then flush it as well
+    if (!isStage2) {
+        stage2Tlb->flushAll();
+    }
+}
+
+void
 TLB::flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
                       bool ignore_el, bool in_host)
 {
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 63928cb..ed621ad 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -246,6 +246,11 @@
     bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
                   Mode mode);

+    /** Reset the entire TLB. Used for CPU switching to prevent stale
+     * translations after multiple switches
+     */
+    void flushAll() override;
+

     /** Reset the entire TLB
      * @param secure_lookup if the operation affects the secure world
@@ -259,15 +264,6 @@
     void flushAllNs(ExceptionLevel target_el, bool ignore_el = false);


-    /** Reset the entire TLB. Used for CPU switching to prevent stale
-     * translations after multiple switches
-     */
-    void flushAll() override
-    {
-        flushAllSecurity(false, EL0, true, false);
-        flushAllSecurity(true, EL0, true, false);
-    }
-
     /** Remove any entries that match both a va and asn
      * @param mva virtual address to flush
      * @param asn contextid/asn to flush on match

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Gerrit-Change-Number: 35239
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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