Pierre Ayoub has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35556 )
Change subject: cpu: Add recursion for DTB entry generation inside BaseCPU
......................................................................
cpu: Add recursion for DTB entry generation inside BaseCPU
Change-Id: Ice93b67ee44a1228120f8a63ad5b9d952f813c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35556
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/BaseCPU.py
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ad91f3a..edd1e33 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -301,6 +301,12 @@
yield cpus_node
+ # Generate nodes from the BaseCPU children (hence under the root
node,
+ # and don't add them as subnode). Please note: this is mainly
needed
+ # for the ISA class, to generate the PMU entry in the DTB.
+ for child_node in self.recurseDeviceTree(state):
+ yield child_node
+
def __init__(self, **kwargs):
super(BaseCPU, self).__init__(**kwargs)
self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ice93b67ee44a1228120f8a63ad5b9d952f813c70
Gerrit-Change-Number: 35556
Gerrit-PatchSet: 3
Gerrit-Owner: Pierre Ayoub <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Pierre Ayoub <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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