Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35938 )
Change subject: misc: Standardize the way create() constructs SimObjects.
......................................................................
misc: Standardize the way create() constructs SimObjects.
The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:
const Params &
Params &
Params *
const Params *
Params const*
This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).
Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/iris/cpu.cc
M src/arch/arm/fastmodel/iris/cpu.hh
M src/arch/arm/fastmodel/iris/interrupts.cc
M src/arch/arm/fastmodel/iris/interrupts.hh
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/fastmodel/iris/tlb.cc
M src/arch/arm/fastmodel/iris/tlb.hh
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/freebsd/fs_workload.hh
M src/arch/arm/freebsd/process.cc
M src/arch/arm/freebsd/process.hh
M src/arch/arm/fs_workload.cc
M src/arch/arm/fs_workload.hh
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/kvm/arm_cpu.hh
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/kvm/base_cpu.cc
M src/arch/arm/kvm/base_cpu.hh
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/linux/fs_workload.hh
M src/arch/arm/linux/process.cc
M src/arch/arm/linux/process.hh
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/nativetrace.hh
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
M src/arch/arm/process.cc
M src/arch/arm/process.hh
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
M src/arch/generic/interrupts.hh
M src/arch/generic/mmu.hh
M src/arch/generic/tlb.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/linux/process.cc
M src/arch/mips/linux/process.hh
M src/arch/mips/mmu.cc
M src/arch/mips/mmu.hh
M src/arch/mips/process.cc
M src/arch/mips/process.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/power/interrupts.cc
M src/arch/power/interrupts.hh
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/linux/process.cc
M src/arch/power/linux/process.hh
M src/arch/power/mmu.cc
M src/arch/power/mmu.hh
M src/arch/power/process.cc
M src/arch/power/process.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/fs_workload.hh
M src/arch/riscv/interrupts.cc
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/linux/process.cc
M src/arch/riscv/linux/process.hh
M src/arch/riscv/mmu.cc
M src/arch/riscv/mmu.hh
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/fs_workload.hh
M src/arch/sparc/interrupts.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/linux/process.cc
M src/arch/sparc/linux/process.hh
M src/arch/sparc/mmu.cc
M src/arch/sparc/mmu.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/nativetrace.hh
M src/arch/sparc/process.cc
M src/arch/sparc/process.hh
M src/arch/sparc/solaris/process.cc
M src/arch/sparc/solaris/process.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/acpi.hh
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/e820.hh
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/intelmp.hh
M src/arch/x86/bios/smbios.cc
M src/arch/x86/bios/smbios.hh
M src/arch/x86/fs_workload.cc
M src/arch/x86/fs_workload.hh
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/x86/linux/fs_workload.cc
M src/arch/x86/linux/fs_workload.hh
M src/arch/x86/linux/process.cc
M src/arch/x86/mmu.cc
M src/arch/x86/mmu.hh
M src/arch/x86/nativetrace.cc
M src/arch/x86/nativetrace.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
M src/arch/x86/process.cc
M src/arch/x86/process.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/base/filters/base.hh
M src/base/filters/block_bloom_filter.cc
M src/base/filters/block_bloom_filter.hh
M src/base/filters/bulk_bloom_filter.cc
M src/base/filters/bulk_bloom_filter.hh
M src/base/filters/h3_bloom_filter.cc
M src/base/filters/h3_bloom_filter.hh
M src/base/filters/multi_bit_sel_bloom_filter.cc
M src/base/filters/multi_bit_sel_bloom_filter.hh
M src/base/filters/multi_bloom_filter.cc
M src/base/filters/multi_bloom_filter.hh
M src/base/filters/perfect_bloom_filter.cc
M src/base/filters/perfect_bloom_filter.hh
M src/base/vnc/vncinput.cc
M src/base/vnc/vncinput.hh
M src/base/vnc/vncserver.cc
M src/base/vnc/vncserver.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/dummy_checker.cc
M src/cpu/dummy_checker.hh
M src/cpu/exetrace.cc
M src/cpu/exetrace.hh
M src/cpu/func_unit.cc
M src/cpu/func_unit.hh
M src/cpu/inst_pb_trace.cc
M src/cpu/inst_pb_trace.hh
M src/cpu/inteltrace.cc
M src/cpu/inteltrace.hh
M src/cpu/intr_control.cc
M src/cpu/intr_control.hh
M src/cpu/intr_control_noisa.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/kvm/vm.cc
M src/cpu/kvm/vm.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/kvm/x86_cpu.hh
M src/cpu/minor/cpu.cc
M src/cpu/minor/cpu.hh
M src/cpu/minor/decode.cc
M src/cpu/minor/decode.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/execute.hh
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch1.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/func_unit.cc
M src/cpu/minor/func_unit.hh
M src/cpu/minor/pipeline.cc
M src/cpu/minor/pipeline.hh
M src/cpu/nativetrace.cc
M src/cpu/nativetrace.hh
M src/cpu/o3/checker.cc
M src/cpu/o3/checker.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/deriv.cc
M src/cpu/o3/deriv.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/fu_pool.cc
M src/cpu/o3/fu_pool.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/probe/simple_trace.cc
M src/cpu/o3/probe/simple_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/pred/2bit_local.cc
M src/cpu/pred/2bit_local.hh
M src/cpu/pred/bi_mode.cc
M src/cpu/pred/bi_mode.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/indirect.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/ltage.cc
M src/cpu/pred/ltage.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.cc
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.cc
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/simple_indirect.cc
M src/cpu/pred/simple_indirect.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage.cc
M src/cpu/pred/tage.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
M src/cpu/pred/tournament.cc
M src/cpu/pred/tournament.hh
M src/cpu/simple/NonCachingSimpleCPU.py
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/probes/simpoint.cc
M src/cpu/simple/probes/simpoint.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/InvalidateGenerator.hh
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/pygen.cc
M src/cpu/testers/traffic_gen/pygen.hh
M src/cpu/testers/traffic_gen/stream_gen.cc
M src/cpu/testers/traffic_gen/stream_gen.hh
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.hh
M src/cpu/timing_expr.cc
M src/cpu/timing_expr.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/dev/arm/a9scu.cc
M src/dev/arm/a9scu.hh
M src/dev/arm/abstract_nvm.hh
M src/dev/arm/amba_device.cc
M src/dev/arm/amba_device.hh
M src/dev/arm/amba_fake.cc
M src/dev/arm/amba_fake.hh
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
M src/dev/arm/display.cc
M src/dev/arm/display.hh
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/flash_device.cc
M src/dev/arm/flash_device.hh
M src/dev/arm/fvp_base_pwr_ctrl.cc
M src/dev/arm/fvp_base_pwr_ctrl.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v2m.cc
M src/dev/arm/gic_v2m.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/gic_v3_its.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gpu_nomali.cc
M src/dev/arm/gpu_nomali.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
M src/dev/arm/pci_host.cc
M src/dev/arm/pci_host.hh
M src/dev/arm/pl011.cc
M src/dev/arm/pl011.hh
M src/dev/arm/pl111.cc
M src/dev/arm/pl111.hh
M src/dev/arm/realview.cc
M src/dev/arm/realview.hh
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/rtc_pl031.hh
M src/dev/arm/rv_ctrl.cc
M src/dev/arm/rv_ctrl.hh
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_deviceifc.cc
M src/dev/arm/smmu_v3_deviceifc.hh
M src/dev/arm/timer_a9global.cc
M src/dev/arm/timer_a9global.hh
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/timer_cpulocal.hh
M src/dev/arm/timer_sp804.cc
M src/dev/arm/timer_sp804.hh
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
M src/dev/arm/vio_mmio.cc
M src/dev/arm/vio_mmio.hh
M src/dev/arm/watchdog_sp805.cc
M src/dev/arm/watchdog_sp805.hh
M src/dev/baddev.cc
M src/dev/baddev.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/hsa/hsa_device.hh
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_driver.hh
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/i2c/bus.cc
M src/dev/i2c/bus.hh
M src/dev/i2c/device.hh
M src/dev/io_device.cc
M src/dev/io_device.hh
M src/dev/isa_fake.cc
M src/dev/isa_fake.hh
M src/dev/mips/malta.cc
M src/dev/mips/malta.hh
M src/dev/mips/malta_cchip.cc
M src/dev/mips/malta_cchip.hh
M src/dev/mips/malta_io.cc
M src/dev/mips/malta_io.hh
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_etherlink.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherbus.hh
M src/dev/net/etherdevice.hh
M src/dev/net/etherdump.cc
M src/dev/net/etherdump.hh
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/ethertap.cc
M src/dev/net/ethertap.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/pci/device.cc
M src/dev/pci/device.hh
M src/dev/pci/host.cc
M src/dev/pci/host.hh
M src/dev/platform.cc
M src/dev/platform.hh
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
M src/dev/serial/serial.cc
M src/dev/serial/serial.hh
M src/dev/serial/simple.cc
M src/dev/serial/simple.hh
M src/dev/serial/terminal.cc
M src/dev/serial/terminal.hh
M src/dev/serial/uart.cc
M src/dev/serial/uart.hh
M src/dev/serial/uart8250.cc
M src/dev/serial/uart8250.hh
M src/dev/sparc/dtod.cc
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M src/dev/sparc/iob.cc
M src/dev/sparc/iob.hh
M src/dev/sparc/mm_disk.cc
M src/dev/sparc/mm_disk.hh
M src/dev/sparc/t1000.cc
M src/dev/sparc/t1000.hh
M src/dev/storage/disk_image.cc
M src/dev/storage/disk_image.hh
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_ctrl.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
M src/dev/storage/simple_disk.cc
M src/dev/storage/simple_disk.hh
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
M src/dev/virtio/block.cc
M src/dev/virtio/block.hh
M src/dev/virtio/console.cc
M src/dev/virtio/console.hh
M src/dev/virtio/fs9p.cc
M src/dev/virtio/fs9p.hh
M src/dev/virtio/pci.cc
M src/dev/virtio/pci.hh
M src/dev/x86/cmos.cc
M src/dev/x86/cmos.hh
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
M src/dev/x86/i82094aa.cc
M src/dev/x86/i82094aa.hh
M src/dev/x86/i8237.cc
M src/dev/x86/i8237.hh
M src/dev/x86/i8254.cc
M src/dev/x86/i8254.hh
M src/dev/x86/i8259.cc
M src/dev/x86/i8259.hh
M src/dev/x86/pc.cc
M src/dev/x86/pc.hh
M src/dev/x86/south_bridge.cc
M src/dev/x86/south_bridge.hh
M src/dev/x86/speaker.cc
M src/dev/x86/speaker.hh
M src/gpu-compute/comm.cc
M src/gpu-compute/comm.hh
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/exec_stage.cc
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M src/gpu-compute/fetch_stage.cc
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M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
M src/gpu-compute/gpu_compute_driver.cc
M src/gpu-compute/gpu_compute_driver.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.cc
M src/gpu-compute/lds_state.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/pool_manager.cc
M src/gpu-compute/pool_manager.hh
M src/gpu-compute/register_file.cc
M src/gpu-compute/register_file.hh
M src/gpu-compute/register_manager.cc
M src/gpu-compute/register_manager.hh
M src/gpu-compute/scalar_memory_pipeline.cc
M src/gpu-compute/scalar_memory_pipeline.hh
M src/gpu-compute/scalar_register_file.cc
M src/gpu-compute/scalar_register_file.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scheduler.cc
M src/gpu-compute/scheduler.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/simple_pool_manager.cc
M src/gpu-compute/simple_pool_manager.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/vector_register_file.cc
M src/gpu-compute/vector_register_file.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
M src/learning_gem5/part2/goodbye_object.cc
M src/learning_gem5/part2/goodbye_object.hh
M src/learning_gem5/part2/hello_object.cc
M src/learning_gem5/part2/hello_object.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.cc
M src/learning_gem5/part2/simple_memobj.hh
M src/learning_gem5/part2/simple_object.cc
M src/learning_gem5/part2/simple_object.hh
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/addr_mapper.cc
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_delta.cc
M src/mem/cache/compressors/base_delta.hh
M src/mem/cache/compressors/base_delta_impl.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/cpack.cc
M src/mem/cache/compressors/cpack.hh
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/dictionary_compressor_impl.hh
M src/mem/cache/compressors/fpcd.cc
M src/mem/cache/compressors/fpcd.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/compressors/perfect.cc
M src/mem/cache/compressors/perfect.hh
M src/mem/cache/compressors/repeated_qwords.cc
M src/mem/cache/compressors/repeated_qwords.hh
M src/mem/cache/compressors/zero.cc
M src/mem/cache/compressors/zero.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/bop.cc
M src/mem/cache/prefetch/bop.hh
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
M src/mem/cache/prefetch/indirect_memory.cc
M src/mem/cache/prefetch/indirect_memory.hh
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/irregular_stream_buffer.hh
M src/mem/cache/prefetch/multi.cc
M src/mem/cache/prefetch/multi.hh
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/pif.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/sbooe.cc
M src/mem/cache/prefetch/sbooe.hh
M src/mem/cache/prefetch/signature_path.cc
M src/mem/cache/prefetch/signature_path.hh
M src/mem/cache/prefetch/signature_path_v2.cc
M src/mem/cache/prefetch/signature_path_v2.hh
M src/mem/cache/prefetch/slim_ampm.cc
M src/mem/cache/prefetch/slim_ampm.hh
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.hh
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/compressed_tags.cc
M src/mem/cache/tags/compressed_tags.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/indexing_policies/base.cc
M src/mem/cache/tags/indexing_policies/base.hh
M src/mem/cache/tags/indexing_policies/set_associative.cc
M src/mem/cache/tags/indexing_policies/set_associative.hh
M src/mem/cache/tags/indexing_policies/skewed_associative.cc
M src/mem/cache/tags/indexing_policies/skewed_associative.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/drampower.cc
M src/mem/drampower.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/external_master.cc
M src/mem/external_master.hh
M src/mem/external_slave.cc
M src/mem/external_slave.hh
M src/mem/hmc_controller.cc
M src/mem/hmc_controller.hh
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/mem_checker_monitor.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
M src/mem/mem_object.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/probes/base.cc
M src/mem/probes/base.hh
M src/mem/probes/mem_footprint.cc
M src/mem/probes/mem_footprint.hh
M src/mem/probes/mem_trace.cc
M src/mem/probes/mem_trace.hh
M src/mem/probes/stack_dist.cc
M src/mem/probes/stack_dist.hh
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
M src/mem/qos/turnaround_policy_ideal.hh
M src/mem/ruby/network/BasicLink.cc
M src/mem/ruby/network/BasicLink.hh
M src/mem/ruby/network/BasicRouter.cc
M src/mem/ruby/network/BasicRouter.hh
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Topology.cc
M src/mem/ruby/network/fault_model/FaultModel.cc
M src/mem/ruby/network/fault_model/FaultModel.hh
M src/mem/ruby/network/garnet/CreditLink.hh
M src/mem/ruby/network/garnet/GarnetLink.cc
M src/mem/ruby/network/garnet/GarnetLink.hh
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/NetworkBridge.cc
M src/mem/ruby/network/garnet/NetworkBridge.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
M src/mem/ruby/network/garnet/NetworkInterface.hh
M src/mem/ruby/network/garnet/NetworkLink.cc
M src/mem/ruby/network/garnet/NetworkLink.hh
M src/mem/ruby/network/garnet/Router.cc
M src/mem/ruby/network/garnet/Router.hh
M src/mem/ruby/network/simple/SimpleLink.cc
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/profiler/Profiler.cc
M src/mem/ruby/profiler/Profiler.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
M src/mem/ruby/structures/RubyPrefetcher.cc
M src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/WireBuffer.cc
M src/mem/ruby/structures/WireBuffer.hh
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/DMASequencer.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/HTMSequencer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubyPortProxy.cc
M src/mem/ruby/system/RubyPortProxy.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/ruby/system/VIPERCoalescer.hh
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/slicc/symbols/StateMachine.py
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
M src/python/m5/SimObject.py
M src/sim/clock_domain.cc
M src/sim/clock_domain.hh
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/dvfs_handler.cc
M src/sim/dvfs_handler.hh
M src/sim/emul_driver.hh
M src/sim/insttracer.hh
M src/sim/kernel_workload.cc
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.cc
M src/sim/power/thermal_node.hh
M src/sim/power_domain.cc
M src/sim/power_domain.hh
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/probe/probe.cc
M src/sim/probe/probe.hh
M src/sim/process.cc
M src/sim/process.hh
M src/sim/pseudo_inst.cc
M src/sim/redirect_path.cc
M src/sim/redirect_path.hh
M src/sim/root.cc
M src/sim/root.hh
M src/sim/se_workload.cc
M src/sim/sim_object.cc
M src/sim/sim_object.hh
M src/sim/sub_system.cc
M src/sim/sub_system.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
M src/sim/voltage_domain.cc
M src/sim/voltage_domain.hh
M src/sim/workload.hh
M src/systemc/core/kernel.cc
M src/systemc/core/kernel.hh
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
817 files changed, 4,064 insertions(+), 4,024 deletions(-)
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Gerrit-Change-Number: 35938
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
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