Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/12278 )
Change subject: cpu-kvm, arch-x86: Fix KVM on Intel platforms
......................................................................
cpu-kvm, arch-x86: Fix KVM on Intel platforms
This is the minimal set of changes from the patch that's been floating
around for a few years originally by Mike Upton.
See http://reviews.gem5.org/r/2613/ and
https://gem5-review.googlesource.com/c/public/gem5/+/7361
The change to the tssDesc is the minimal change to get KVM working on
Intel platforms. However, the other changes seem prudent to add.
Tested on both Intel (i7-7700) and AMD (EPYC 7451) platforms.
Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12278
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbr...@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Gabe Black <gabebl...@google.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/x86/fs_workload.cc
1 file changed, 12 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc
index b66ddfd..a69e50b 100644
--- a/src/arch/x86/fs_workload.cc
+++ b/src/arch/x86/fs_workload.cc
@@ -189,6 +189,12 @@
// 32 bit data segment
SegDescriptor dsDesc = initDesc;
+ dsDesc.type.e = 0;
+ dsDesc.type.w = 1;
+ dsDesc.d = 1;
+ dsDesc.baseHigh = 0;
+ dsDesc.baseLow = 0;
+
uint64_t dsDescVal = dsDesc;
phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
@@ -204,10 +210,16 @@
tc->setMiscReg(MISCREG_SS, (RegVal)ds);
tc->setMiscReg(MISCREG_TSL, 0);
+ SegAttr ldtAttr = 0;
+ ldtAttr.unusable = 1;
+ tc->setMiscReg(MISCREG_TSL_ATTR, ldtAttr);
tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
SegDescriptor tssDesc = initDesc;
+ tssDesc.type = 0xB;
+ tssDesc.s = 0;
+
uint64_t tssDescVal = tssDesc;
phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Gerrit-Change-Number: 12278
Gerrit-PatchSet: 5
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Alexandru Duțu <alexandru.d...@amd.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-Reviewer: mike upton <michaelup...@gmail.com>
Gerrit-CC: Swapnil Haria <swapnils...@gmail.com>
Gerrit-MessageType: merged
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