Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35242 )
Change subject: arch-arm: Add el2Enabled cached variable
......................................................................
arch-arm: Add el2Enabled cached variable
Several TLB invalidation instructions rely on VMID matching. This is
only applicable is EL2 is implemented and enabled in the current state.
The code prior to this patch was making the now invalid assumption that
we shouldn't consider the VMID if we are doing a secure lookup. This is
because in the past if we were in secure mode we were sure EL2 was not
enabled.
This is fishy and not valid anymore anyway after the introduction of
secure EL2.
Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35242
Reviewed-by: Nikos Nikoleris <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
4 files changed, 15 insertions(+), 6 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3607c29..1866319 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1803,7 +1803,6 @@
// VAEx(IS) and VALEx(IS) are the same because TLBs
// only store entries
// from the last level of translation table walks
- // @todo: handle VMID to enable Virtualization
// AArch64 TLB Invalidate by VA, EL3
case MISCREG_TLBI_VAE3_Xt:
case MISCREG_TLBI_VALE3_Xt:
@@ -1895,7 +1894,6 @@
return;
}
// AArch64 TLB Invalidate by ASID, EL1
- // @todo: handle VMID to enable Virtualization
case MISCREG_TLBI_ASIDE1_Xt:
{
assert64();
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 0e61186..38aa38e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -281,7 +281,7 @@
const bool el_match = te->checkELMatch(
tlbi_op.targetEL, tlbi_op.inHost);
if (te->valid && tlbi_op.secureLookup == !te->nstid &&
- (te->vmid == vmid || tlbi_op.secureLookup) && el_match) {
+ (te->vmid == vmid || tlbi_op.el2Enabled) && el_match) {
DPRINTF(TLB, " - %s\n", te->print());
te->valid = false;
@@ -383,7 +383,7 @@
te = &table[x];
if (te->valid && te->asid == tlbi_op.asid &&
tlbi_op.secureLookup == !te->nstid &&
- (te->vmid == vmid || tlbi_op.secureLookup) &&
+ (te->vmid == vmid || tlbi_op.el2Enabled) &&
te->checkELMatch(tlbi_op.targetEL, tlbi_op.inHost)) {
te->valid = false;
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index be7a78b..bb5153d 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -47,6 +47,8 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
+ el2Enabled = EL2Enabled(tc);
+
getMMUPtr(tc)->flush(*this);
// If CheckerCPU is connected, need to notify it of a flush
@@ -59,12 +61,14 @@
void
ITLBIALL::operator()(ThreadContext* tc)
{
+ el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->iflush(*this);
}
void
DTLBIALL::operator()(ThreadContext* tc)
{
+ el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->dflush(*this);
}
@@ -87,6 +91,8 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
+ el2Enabled = EL2Enabled(tc);
+
getMMUPtr(tc)->flush(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
@@ -97,12 +103,14 @@
void
ITLBIASID::operator()(ThreadContext* tc)
{
+ el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->iflush(*this);
}
void
DTLBIASID::operator()(ThreadContext* tc)
{
+ el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->dflush(*this);
}
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 8b40587..888cd99 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -81,7 +81,7 @@
{
public:
TLBIALL(ExceptionLevel _targetEL, bool _secure)
- : TLBIOp(_targetEL, _secure), inHost(false)
+ : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false)
{}
void operator()(ThreadContext* tc) override;
@@ -93,6 +93,7 @@
}
bool inHost;
+ bool el2Enabled;
};
/** Instruction TLB Invalidate All */
@@ -145,13 +146,15 @@
{
public:
TLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
- : TLBIOp(_targetEL, _secure), asid(_asid), inHost(false)
+ : TLBIOp(_targetEL, _secure), asid(_asid), inHost(false),
+ el2Enabled(false)
{}
void operator()(ThreadContext* tc) override;
uint16_t asid;
bool inHost;
+ bool el2Enabled;
};
/** Instruction TLB Invalidate by ASID match */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Gerrit-Change-Number: 35242
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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