Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35246 )
Change subject: arch-arm: Do not use _flushMva for TLBI IPA
......................................................................
arch-arm: Do not use _flushMva for TLBI IPA
This is just a cosmetic change
Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35246
Reviewed-by: Nikos Nikoleris <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.hh
2 files changed, 10 insertions(+), 2 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 04b5cd4..5d2ed90 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -463,8 +463,9 @@
TLB::flush(const TLBIIPA &tlbi_op)
{
assert(!isStage2);
- stage2Tlb->_flushMva(tlbi_op.addr, 0xbeef, tlbi_op.secureLookup,
- true, tlbi_op.targetEL, false);
+
+ // Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
+ stage2Tlb->flush(tlbi_op.makeStage2());
}
void
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index cab0e52..ce72dfb 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -292,6 +292,13 @@
void operator()(ThreadContext* tc) override;
+ /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
+ TLBIMVAA
+ makeStage2() const
+ {
+ return TLBIMVAA(EL1, secureLookup, addr);
+ }
+
Addr addr;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Gerrit-Change-Number: 35246
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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