Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36979 )
Change subject: cpu: Make the SimpleAtomic cpu use a back door for fetch.
......................................................................
cpu: Make the SimpleAtomic cpu use a back door for fetch.
If the memory system can provide a back door to memory, store that, and
use it for subsequent accesses to the range it covers. For now, this
covers only fetch. That's because fetch will generally happen more than
loads and stores, and because it's relatively simple to implement since
we can ignore atomic operations, etc.
Some limitted benchmarking suggests that this speeds up x86 linux boot
by about 20%, although my modifications to the config to remove caching
(which blocks the back door mechanism) also made gem5 crash, so it's
hard to say for sure if that's a valid result. The crash happened in the
same way before and after, so it's probably at least relatively
representative.
While this gives a pretty substantial performance boost, it will prevent
statistics from being collected at the memory, or on intermediate objects
in the interconnect like the bus. We may want to add some way to toggle
it on or off, in case someone cares about those sorts of stats in atomic
mode. It's probably not *too* urgent, since memory performance from
atomic mode is approximate at best to begin with.
Change-Id: I73f73017e454300fd4d61f58462eb4ec719b8d85
---
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8658353..e610b2c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -269,7 +269,26 @@
Tick
AtomicSimpleCPU::sendPacket(RequestPort &port, const PacketPtr &pkt)
{
- return port.sendAtomic(pkt);
+ MemBackdoorPtr bd = nullptr;
+ Tick latency = port.sendAtomicBackdoor(pkt, bd);
+
+ // If the target gave us a backdoor for next time and we didn't
+ // already have it, record it.
+ if (bd && memBackdoors.insert(bd->range(), bd) != memBackdoors.end()) {
+ // Install a callback to erase this backdoor if it goes away.
+ auto callback = [this](const MemBackdoor &backdoor) {
+ for (auto it = memBackdoors.begin();
+ it != memBackdoors.end(); it++) {
+ if (it->second == &backdoor) {
+ memBackdoors.erase(it);
+ return;
+ }
+ }
+ panic("Got invalidation for unknown memory backdoor.");
+ };
+ bd->addInvalidationCallback(callback);
+ }
+ return latency;
}
Tick
@@ -661,15 +680,24 @@
//if (decoder.needMoreBytes())
//{
icache_access = true;
- Packet ifetch_pkt = Packet(ifetch_req,
MemCmd::ReadReq);
- ifetch_pkt.dataStatic(&inst);
+ auto bd_it =
memBackdoors.contains(ifetch_req->getPaddr());
+ if (bd_it != memBackdoors.end()) {
+ auto *bd = bd_it->second;
+ Addr offset = ifetch_req->getPaddr() -
+ bd->range().start();
+ memcpy(&inst, bd->ptr() + offset,
+ ifetch_req->getSize());
+ } else {
+ Packet pkt = Packet(ifetch_req, MemCmd::ReadReq);
+ pkt.dataStatic(&inst);
- icache_latency = sendPacket(icachePort, &ifetch_pkt);
+ icache_latency = sendPacket(icachePort, &pkt);
- assert(!ifetch_pkt.isError());
+ assert(!pkt.isError());
- // ifetch_req is initialized to read the instruction
- // directly into the CPU object's inst field.
+ // ifetch_req is initialized to read the
instruction
+ // directly into the CPU object's inst field.
+ }
//}
}
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 7c7269a..7dc0bdf 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -41,8 +41,10 @@
#ifndef __CPU_SIMPLE_ATOMIC_HH__
#define __CPU_SIMPLE_ATOMIC_HH__
+#include "base/addr_range_map.hh"
#include "cpu/simple/base.hh"
#include "cpu/simple/exec_context.hh"
+#include "mem/backdoor.hh"
#include "mem/request.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/probe/probe.hh"
@@ -57,6 +59,7 @@
void init() override;
protected:
+ AddrRangeMap<MemBackdoorPtr, 1> memBackdoors;
EventFunctionWrapper tickEvent;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36979
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I73f73017e454300fd4d61f58462eb4ec719b8d85
Gerrit-Change-Number: 36979
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
