Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31417 )
Change subject: mem-ruby: functions for connecting sequencer ports
......................................................................
mem-ruby: functions for connecting sequencer ports
Added functions for connecting the sequencer and cpu ports.
Using these functions instead of wiring up the ports directly allow
protocols to provide specialized sequencer implementations. For
instance, connecting the cpu icache_port and dcache_port to
different sequencer ports or to different sequencers.
A follow-up patch will update the configurations to use these
functions.
Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b
Signed-off-by: Tiago Mück <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/mem/ruby/system/Sequencer.py
1 file changed, 26 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 0e23fc0..f56574c 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -99,6 +99,32 @@
# 99 is the dummy default value
coreid = Param.Int(99, "CorePair core id")
+ def connectCpuPorts(self, cpu):
+ """
+ Helper for connecting all cpu memory request output ports to this
+ object's in_ports.
+ This assumes the provided cpu object is an instance of BaseCPU.
Non-cpu
+ objects should use connectInstPort and connectDataPort.
+ """
+ import m5.objects
+ assert(isinstance(cpu, m5.objects.BaseCPU))
+ # this connects all cpu mem-side ports to self.in_ports
+ cpu.connectAllPorts(self)
+
+ def connectIOPorts(self, piobus):
+ """
+ Helper for connecting this object's IO request and response ports to
the
+ provided bus object. Usually a iobus object is used to wireup IO
+ components in a full system simulation. Incoming/Outgoing IO
requests do
+ not go though the SLICC protocol so the iobus must be connected to
the
+ sequencer directly.
+ """
+ import m5.defines
+ self.pio_request_port = piobus.cpu_side_ports
+ self.mem_request_port = piobus.cpu_side_ports
+ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+ self.pio_response_port = piobus.mem_side_ports
+
class RubyHTMSequencer(RubySequencer):
type = 'RubyHTMSequencer'
cxx_class = 'HTMSequencer'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b
Gerrit-Change-Number: 31417
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück <[email protected]>
Gerrit-Reviewer: Bradford Beckmann <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Tiago Mück <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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