Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38389 )
Change subject: arch: Get rid of global maximums for numbers of
source/dest/misc regs.
......................................................................
arch: Get rid of global maximums for numbers of source/dest/misc regs.
Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
---
M src/arch/SConscript
M src/arch/arm/registers.hh
M src/arch/isa_parser/isa_parser.py
M src/arch/isa_parser/operand_list.py
M src/arch/mips/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
9 files changed, 7 insertions(+), 55 deletions(-)
diff --git a/src/arch/SConscript b/src/arch/SConscript
index b97881d..a4825e5 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -185,8 +185,6 @@
add_gen('exec-g.cc.inc')
add_gen('exec-ns.cc.inc')
- add_gen('max_inst_regs.hh')
-
# These generated files are also top level sources.
def source_gen(name):
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 630a145..0955906 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -42,22 +42,14 @@
#define __ARCH_ARM_REGISTERS_HH__
#include "arch/arm/ccregs.hh"
-#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-namespace ArmISA {
-
-
-// For a predicated instruction, we need all the
-// destination registers to also be sources
-const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
- ArmISAInst::MaxInstSrcRegs;
-using ArmISAInst::MaxInstDestRegs;
-using ArmISAInst::MaxMiscDestRegs;
+namespace ArmISA
+{
// Number of VecElem per Vector Register considering only pre-SVE
// Advanced SIMD registers.
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index 9ca813e..53348df 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -526,8 +526,6 @@
symbols = ('makeList', 're')
self.exportContext = dict([(s, eval(s)) for s in symbols])
- self.maxInstSrcRegs = 0
- self.maxInstDestRegs = 0
self.maxMiscDestRegs = 0
def operandsRE(self):
@@ -677,13 +675,6 @@
print('#include "%s"' % fn, file=f)
print('}', file=f)
- # max_inst_regs.hh
- self.update('max_inst_regs.hh',
- '''namespace %(namespace)s {
- const int MaxInstSrcRegs = %(maxInstSrcRegs)d;
- const int MaxInstDestRegs = %(maxInstDestRegs)d;
- const int MaxMiscDestRegs = %(maxMiscDestRegs)d;\n}\n''' % self)
-
scaremonger_template ='''// DO NOT EDIT
// This file was automatically generated from an ISA description:
// %(filename)s
diff --git a/src/arch/isa_parser/operand_list.py
b/src/arch/isa_parser/operand_list.py
index cea3ae4..3da7386 100755
--- a/src/arch/isa_parser/operand_list.py
+++ b/src/arch/isa_parser/operand_list.py
@@ -133,11 +133,6 @@
self.predRead = any(i.hasReadPred() for i in self.items)
self.predWrite = any(i.hasWritePred() for i in self.items)
- parser.maxInstSrcRegs = max(parser.maxInstSrcRegs, self.numSrcRegs)
- parser.maxInstDestRegs = max(parser.maxInstDestRegs,
self.numDestRegs)
- parser.maxMiscDestRegs = max(parser.maxMiscDestRegs,
- self.numMiscDestRegs)
-
# now make a final pass to finalize op_desc fields that may depend
# on the register enumeration
for op_desc in self.items:
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index aaebf35..3deef88 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -32,7 +32,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/mips/generated/max_inst_regs.hh"
#include "base/logging.hh"
#include "base/types.hh"
@@ -41,10 +40,6 @@
namespace MipsISA
{
-using MipsISAInst::MaxInstSrcRegs;
-using MipsISAInst::MaxInstDestRegs;
-using MipsISAInst::MaxMiscDestRegs;
-
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
const int NumIntSpecialRegs = 9;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index a6d28a8..b5a3321 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -31,18 +31,11 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/power/generated/max_inst_regs.hh"
#include "arch/power/miscregs.hh"
#include "base/types.hh"
-namespace PowerISA {
-
-using PowerISAInst::MaxInstSrcRegs;
-using PowerISAInst::MaxInstDestRegs;
-
-// Power writes a misc register outside of the isa parser, so it can't
-// be detected by it. Manually add it here.
-const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
+namespace PowerISA
+{
// Not applicable to Power
using VecElem = ::DummyVecElem;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index ed8b916..c0cc4ed 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -52,15 +52,11 @@
#include "arch/generic/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/riscv/generated/max_inst_regs.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
-namespace RiscvISA {
-
-using RiscvISAInst::MaxInstSrcRegs;
-using RiscvISAInst::MaxInstDestRegs;
-const int MaxMiscDestRegs = 2;
+namespace RiscvISA
+{
// Not applicable to RISC-V
using VecElem = ::DummyVecElem;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 6fd6577..0602176 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -31,7 +31,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/sparc/generated/max_inst_regs.hh"
#include "arch/sparc/miscregs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "base/types.hh"
@@ -39,10 +38,6 @@
namespace SparcISA
{
-using SparcISAInst::MaxInstSrcRegs;
-using SparcISAInst::MaxInstDestRegs;
-using SparcISAInst::MaxMiscDestRegs;
-
// Not applicable to SPARC
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c041a07..74cc528 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,7 +41,6 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/x86/generated/max_inst_regs.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/misc.hh"
@@ -49,9 +48,7 @@
namespace X86ISA
{
-using X86ISAInst::MaxInstSrcRegs;
-using X86ISAInst::MaxInstDestRegs;
-using X86ISAInst::MaxMiscDestRegs;
+
const int NumMiscRegs = NUM_MISCREGS;
const int NumIntArchRegs = NUM_INTREGS;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38389
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
Gerrit-Change-Number: 38389
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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