Huang Jiasen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38576 )
Change subject: ISA: Extended Instructions adopted in RISCV arch XUANTIE
C910 CPU
......................................................................
ISA: Extended Instructions adopted in RISCV arch XUANTIE C910 CPU
Change-Id: I3fdf1dfbd0c0a88d4cc03b3663660265b9f78d76
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 186 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 5ef68fe..009dd70 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -418,10 +418,193 @@
}
}
+ 0x02: decode FUNCT3 { // FUNCT3: <14:12>
+ format ROp {
+ 0x2: ext({{
+ uint32_t msb = FUNCT6; // <31:26>
+ uint32_t lsb = SHAMT6; // <25:20>
+ uint64_t mask = 0xffffffffffffffff;
+ Rs1 = (Rs1 << (63 - msb));
+ Rs1 = (Rs1 >> (63 - msb));
+ Rs1 = Rs1 >> lsb;
+ if ((msb - lsb + 1) > 63) { mask = 0; }
+ else {
+ mask = mask >> (msb - lsb + 1);
+ mask = mask << (msb - lsb + 1);
+ }
+
+ if (Rs1 >> (msb - lsb)) { Rs1 = Rs1 | mask; }
+
+ Rd = Rs1;
+ }});
+ 0x3: extu({{
+ uint32_t msb = FUNCT6; // <31:26>
+ uint32_t lsb = SHAMT6; // <25:20>
+ Rs1 = (Rs1 << (63 - msb));
+ Rs1 = (Rs1 >> (63 - msb));
+ Rs1 = (Rs1 >> lsb);
+ Rd = Rs1;
+ }});
+ 0x1: decode FUNCT5 { // FUNCT5: <31:27>
+ 0x0: addsl({{
+ Rd = Rs1 + (Rs2 << FUNCT2);
+ }});
+ 0x2: decode FUNCT2_HI {
+ 0x0: srri({{
+ Rd = Rs1 >> SHAMT6;
+ Rd = Rd | (Rs1 << (64 - SHAMT6));
+ }});
+ 0x1: decode FUNCT2_LO {
+ 0x0: srriw({{
+ uint32_t op1_tmp = Rs1_sd & 0xffffffff;
+ uint32_t imm_use = RS2 & 0x1f;
+ uint32_t result = (op1_tmp >> imm_use);
+ result = result | (op1_tmp << (32 -
imm_use));
+ // Rd = (result & 0x80000000) ?
(0xffffffff00000000 | result) : (result & 0x00000000ffffffff); // Exactly
the same as (int32_t)(result)
+ Rd = (int32_t)(result);
+ }});
+ }
+ }
+ 0x4: decode FUNCT2 {
+ 0x0: mula({{
+ if (Rs2_sd == 0) {
+ Rd = Rs1_sd;
+ printf("mveqz::execute\n");
+ } else {
+ uint64_t tmp = (Rs1_sd * Rs2_sd) &
0xffffffffffffffff;
+ uint64_t tmp_Rd = Rd;
+ printf("~~~~~~~~~~~~~~~~~~~~~mula::execute
(rs1 * rs2)[63:0]_hi_32 = %x (rs1 * rs2)[63:0]_lo_32 = %x tmp_Rd_hi_32 = %x
tmp_Rd_lo_32 = %x\n", (int32_t)((tmp >> 32) & 0xffffffff), (int32_t)(tmp &
0xffffffff), (int32_t)((tmp_Rd >> 32) & 0xffffffff), (int32_t)(tmp_Rd &
0xffffffff));
+ Rd = Rd + tmp;
+ printf("Rd_hi_32 = %x Rd_lo_32 = %x\n",
(int32_t)((Rd >> 32) & 0xffffffff), (int32_t)(Rd & 0xffffffff));
+ }
+ }}, IntMultOp);
+ 0x1: muls({{
+ uint64_t tmp = (Rs1_sd * Rs2_sd) &
0xffffffffffffffff;
+ uint64_t tmp_Rd = Rd;
+ printf("~~~~~~~~~~~~~~~~~~~~~muls::execute
(rs1 * rs2)[63:0]_hi_32 = %x (rs1 * rs2)[63:0]_lo_32 = %x tmp_Rd_hi_32 = %x
tmp_Rd_lo_32 = %x\n", (int32_t)((tmp >> 32) & 0xffffffff), (int32_t)(tmp &
0xffffffff), (int32_t)((tmp_Rd >> 32) & 0xffffffff), (int32_t)(tmp_Rd &
0xffffffff));
+ Rd = Rd - tmp;
+ printf("Rd_hi_32 = %x Rd_lo_32 = %x\n",
(int32_t)((Rd >> 32) & 0xffffffff), (int32_t)(Rd & 0xffffffff));
+ }}, IntMultOp);
+ 0x2: mulaw({{
+// int64_t tmp = (Rd_sd & 0xffffffff) +
(int32_t)((int32_t)(Rs1_sd & 0xffffffff) * (int32_t)(Rs2_sd & 0xffffffff));
+ int64_t tmp = (Rd_sd & 0xffffffff) +
(int32_t)((Rs1_sd & 0xffffffff) * (Rs2_sd & 0xffffffff));
+ int32_t tmp_lo_32 = tmp & 0xffffffff;
+ Rd_sd = (int32_t)(tmp_lo_32);
+ printf("Mulaw::execute rs1[31:0] = %x
rs2[31:0] = %x rs1[31:0] * rs2[31:0] = %x tmp_lo_32 = %x\n",
(int32_t)(Rs1_sd & 0xffffffff), (int32_t)(Rs2_sd & 0xffffffff),
(int32_t)((int16_t)(Rs1_sd & 0xffff) * (int16_t)(Rs2_sd & 0xffff)),
tmp_lo_32);
+ }}, IntMultOp);
+ 0x3: mulsw({{
+ int64_t tmp = (Rd_sd & 0xffffffff) -
(int32_t)((Rs1_sd & 0xffffffff) * (Rs2_sd & 0xffffffff));
+ int32_t tmp_lo_32 = tmp & 0xffffffff;
+ Rd_sd = (int32_t)(tmp_lo_32);
+ printf("Mulsw::execute rs1[31:0] = %x
rs2[31:0] = %x rs1[31:0] * rs2[31:0] = %x tmp_lo_32 = %x\n",
(int32_t)(Rs1_sd & 0xffffffff), (int32_t)(Rs2_sd & 0xffffffff),
(int32_t)((int16_t)(Rs1_sd & 0xffff) * (int16_t)(Rs2_sd & 0xffff)),
tmp_lo_32);
+ }}, IntMultOp);
+ }
+ 0x5: decode FUNCT2 {
+ 0x0: mulah({{
+ int64_t tmp = (Rd_sd & 0xffffffff) +
(int32_t)((int16_t)(Rs1_sd & 0xffff) * (int16_t)(Rs2_sd & 0xffff));
+ int32_t tmp_lo_32 = tmp & 0xffffffff;
+ Rd_sd = (int32_t)(tmp_lo_32);
+ printf("Mulah::execute rs1[15:0] * rs2[15:0]
= %x tmp_lo_32 = %x\n", (int32_t)((int16_t)(Rs1_sd & 0xffff) *
(int16_t)(Rs2_sd & 0xffff)), tmp_lo_32);
+ }}, IntMultOp);
+ 0x1: mulsh({{
+ int64_t tmp = (Rd_sd & 0xffffffff) -
(int32_t)((int16_t)(Rs1_sd & 0xffff) * (int16_t)(Rs2_sd & 0xffff));
+ int32_t tmp_lo_32 = tmp & 0xffffffff;
+ Rd_sd = (int32_t)(tmp_lo_32);
+ printf("Mulsh::execute rs1[15:0] * rs2[15:0]
= %x tmp_lo_32 = %x\n", (int32_t)((int16_t)(Rs1_sd & 0xffff) *
(int16_t)(Rs2_sd & 0xffff)), tmp_lo_32);
+ }}, IntMultOp);
+ }
+ 0x8: decode FUNCT2 {
+ 0x1: mvnez({{
+ if (Rs2_sd) {
+ Rd_sd = Rs1_sd;
+ printf("mvnez::execute\n");
+ }
+ }}, IntMultOp);
+ }
+ 0x11: decode FUNCT2_HI { // FUNCT2_HI: <26>
+ 0x0: tst({{
+ bool result = (Rs1 >> SHAMT6) & 0x1; //
SHAMT6: <25:20>
+ Rd = result;
+ }});
+ }
+ 0x10: decode RS2 { // RS2: <24:20>
+ 0x0: decode FUNCT2 { // FUNCT2: <26:25>
+ 0x0: tstnbz({{
+ Rd = 0;
+ if(!(Rs1 & 0xff00000000000000)) {
+// printf("Rs1 & 0xff00000000000000 ==
0\n");
+ Rd = Rd | 0xff00000000000000;
+ }
+ if(!(Rs1 & 0x00ff000000000000)) {Rd = Rd |
0x00ff000000000000;}
+ if(!(Rs1 & 0x0000ff0000000000)) {Rd = Rd |
0x0000ff0000000000;}
+ if(!(Rs1 & 0x000000ff00000000)) {Rd = Rd |
0x000000ff00000000;}
+ if(!(Rs1 & 0x00000000ff000000)) {Rd = Rd |
0x00000000ff000000;}
+ if(!(Rs1 & 0x0000000000ff0000)) {Rd = Rd |
0x0000000000ff0000;}
+ if(!(Rs1 & 0x000000000000ff00)) {Rd = Rd |
0x000000000000ff00;}
+ if(!(Rs1 & 0x00000000000000ff)) {Rd = Rd |
0x00000000000000ff;}
+ }});
+ 0x1: rev({{
+ uint64_t op1 = Rs1;
+ uint64_t oper7_0 = op1 & 0xff;
+ uint64_t oper15_8 = (op1 >> 8) & 0xff;
+ uint64_t oper23_16 = (op1 >> 16) & 0xff;
+ uint64_t oper31_24 = (op1 >> 24) & 0xff;
+ uint64_t oper39_32 = (op1 >> 32) & 0xff;
+ uint64_t oper47_40 = (op1 >> 40) & 0xff;
+ uint64_t oper55_48 = (op1 >> 48) & 0xff;
+ uint64_t oper63_56 = (op1 >> 56) & 0xff;
+ printf("rev::execute <63:56>_hi = %x
<63:56>_lo = %x\n", (int32_t)((oper63_56 & 0xffffffff00000000) >> 32),
(int32_t)(oper63_56 & 0xffffffff));
+ printf("rev::execute <7:0>_hi = %x
<7:0>_lo = %x\n", (int32_t)((oper7_0 & 0xffffffff00000000) >> 32),
(int32_t)(oper7_0 & 0xffffffff));
+ Rd = (oper7_0 << 56) | (oper15_8 << 48) |
(oper23_16 << 40) | (oper31_24 << 32) | (oper39_32 << 24) | (oper47_40 <<
16) | (oper55_48 << 8) | (oper63_56 << 0);
+ }});
+ 0x2: ff0({{
+ uint32_t ff0 = 0;
+ uint64_t op1 = Rs1_ud;
+ int i;
+ for(i = 0; i < 64; ++i) {
+ if(!(op1 >> (63 - i) & 0x1)){
+ break;
+ }
+ }
+ ff0 = (i >= 64) ? 64 : i;
+ Rd_uw = ff0;
+ }});
+ 0x3: ff1({{
+ uint32_t ff1 = 0;
+ uint64_t op1 = Rs1_ud;
+ int i;
+ for(i = 0; i < 64; ++i) {
+ if((op1 >> (63 - i) & 0x1)){
+ break;
+ }
+ }
+ ff1 = (i >= 64) ? 64 : i;
+ Rd_uw = ff1;
+ }});
+ }
+ }
+ 0x12: decode RS2 {
+ 0x0: decode FUNCT2 {
+ 0x0: revw({{
+ uint64_t op1 = Rs1;
+ uint64_t oper7_0 = op1 & 0xff;
+ uint64_t oper15_8 = (op1 >> 8) & 0xff;
+ uint64_t oper23_16 = (op1 >> 16) & 0xff;
+ uint64_t oper31_24 = (op1 >> 24) & 0xff;
+ uint64_t result = (oper7_0 << 24) |
(oper15_8 << 16) | (oper23_16 << 8) | oper31_24;
+ result = (result & 0x80000000) ?
(0xffffffff00000000 | result) : (result & 0xffffffff);
+ Rd = result;
+ }});
+ }
+ }
+ }
+ }
+ }
+
0x03: decode FUNCT3 {
format FenceOp {
0x0: fence({{
- }}, uint64_t, IsReadBarrier, IsWriteBarrier, No_OpClass);
+ }}, uint64_t, IsMemBarrier, No_OpClass);
0x1: fence_i({{
}}, uint64_t, IsNonSpeculative, IsSerializeAfter,
No_OpClass);
}
@@ -1848,7 +2031,8 @@
"sfence in user mode or TVM
enabled",
machInst);
}
- xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
+ xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
+ xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
0x18: mret({{
if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38576
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3fdf1dfbd0c0a88d4cc03b3663660265b9f78d76
Gerrit-Change-Number: 38576
Gerrit-PatchSet: 1
Gerrit-Owner: Huang Jiasen <jiasen....@alibaba-inc.com>
Gerrit-MessageType: newchange
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