Cui Jin has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38578 )
Change subject: arch-riscv: fix MIE csr register setting bugs
......................................................................
arch-riscv: fix MIE csr register setting bugs
Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.
The fix is verified in FS.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-855
Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 72f7dc1..b95af76 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -383,9 +383,9 @@
xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
break;
case CSR_MIP: case CSR_MIE:
- if (oldinterrupt.mei == newinterrupt.mei &&
- oldinterrupt.mti == newinterrupt.mti &&
- oldinterrupt.msi == newinterrupt.msi) {
+ if (oldinterrupt.mei != newinterrupt.mei ||
+ oldinterrupt.mti != newinterrupt.mti ||
+ oldinterrupt.msi != newinterrupt.msi) {
xc->setMiscReg(CSRData.at(csr).physIndex,data);
} else {
std::string error = "Interrupt m bits are "
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Gerrit-Change-Number: 38578
Gerrit-PatchSet: 1
Gerrit-Owner: Cui Jin <[email protected]>
Gerrit-MessageType: newchange
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