Cui Jin has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38755 )
Change subject: arch-riscv: fix the wrong cause register setting
......................................................................
arch-riscv: fix the wrong cause register setting
The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.
Minor bug is for the mpie is suppossed to be set to the value of
old mie.
The fix is verified in FS.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-858
Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
---
M src/arch/riscv/faults.cc
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index ac4c582..9f0b9a1 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -113,7 +113,7 @@
tval = MISCREG_MTVAL;
status.mpp = pp;
- status.mpie = status.sie;
+ status.mpie = status.mie;
status.mie = 0;
break;
default:
@@ -123,7 +123,8 @@
// Set fault cause, privilege, and return PC
tc->setMiscReg(cause,
- (isInterrupt() << (sizeof(uint64_t) * 4 - 1)) |
_code);
+ ((uint64_t)isInterrupt() << (sizeof(uint64_t) * 8 -
1))
+ | _code);
tc->setMiscReg(epc, tc->instAddr());
tc->setMiscReg(tval, trap_value());
tc->setMiscReg(MISCREG_PRV, prv);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Gerrit-Change-Number: 38755
Gerrit-PatchSet: 1
Gerrit-Owner: Cui Jin <cuij...@huawei.com>
Gerrit-MessageType: newchange
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