Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39323 )
Change subject: arch,cpu: Move the inUserMode function to the ISA object.
......................................................................
arch,cpu: Move the inUserMode function to the ISA object.
This function is used when tracing execution with --debug-flags=Exec.
The data used by the function (now method) is stored in the ISA object,
and so that's a logical place to move it.
Change-Id: I624f9365124679343e988cabfb4e1929225b439a
---
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/isa.hh
M src/arch/power/utility.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/isa.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
15 files changed, 66 insertions(+), 65 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/isa.hh
b/src/arch/arm/fastmodel/iris/isa.hh
index d9646df..a7ae7b5 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -28,6 +28,7 @@
#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
namespace Iris
@@ -39,6 +40,13 @@
ISA(const Params &p) : BaseISA(p) {}
void serialize(CheckpointOut &cp) const;
+
+ bool
+ inUserMode() const override
+ {
+ CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+ return ::inUserMode(cpsr);
+ }
};
} // namespace Iris
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 97b41cc..d350378 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,6 +48,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
+#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
#include "arch/generic/traits.hh"
#include "debug/Checkpoint.hh"
@@ -892,6 +893,13 @@
{
return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
}
+
+ bool
+ inUserMode() const override
+ {
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ return ArmISA::inUserMode(cpsr);
+ }
};
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index e255b1c..bd043df 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -111,23 +111,11 @@
}
static inline bool
-inUserMode(ThreadContext *tc)
-{
- return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
-}
-
-static inline bool
inPrivilegedMode(CPSR cpsr)
{
return !inUserMode(cpsr);
}
-static inline bool
-inPrivilegedMode(ThreadContext *tc)
-{
- return !inUserMode(tc);
-}
-
bool isSecure(ThreadContext *tc);
bool inAArch64(ThreadContext *tc);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 9ea2d9f..12c58ad 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -59,6 +59,7 @@
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
virtual uint64_t getExecutingAsid() const { return 0; }
+ virtual bool inUserMode() const = 0;
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 1b81046..6242c62 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -142,6 +142,26 @@
// dummy
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
+
+ bool
+ inUserMode() const override
+ {
+ RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS);
+ RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG);
+
+ if (// EXL, ERL or CU0 set, CP0 accessible
+ (Stat & 0x10000006) == 0 &&
+ // DM bit set, CP0 accessible
+ (Dbg & 0x40000000) == 0 &&
+ // KSU = 0, kernel mode is base mode
+ (Stat & 0x00000018) != 0) {
+ // Unable to use Status_CU0, etc directly,
+ // using bitfields & masks.
+ return true;
+ } else {
+ return false;
+ }
+ }
};
}
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 0cb9349..6fb211d 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -65,22 +65,6 @@
bool isQnan(void *val_ptr, int size);
bool isSnan(void *val_ptr, int size);
-static inline bool
-inUserMode(ThreadContext *tc)
-{
- RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
- RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
-
- if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
- (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
- (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
- // Unable to use Status_CU0, etc directly, using bitfields & masks
- return true;
- } else {
- return false;
- }
-}
-
////////////////////////////////////////////////////////////////////////
//
// Translation stuff
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 1fbbddf..0d00ec1 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -128,6 +128,12 @@
return reg;
}
+ bool
+ inUserMode() const override
+ {
+ return false;
+ }
+
const Params ¶ms() const;
ISA(const Params &p);
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 9092a23..bdb201d 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -58,12 +58,6 @@
pc.advance();
}
-static inline bool
-inUserMode(ThreadContext *tc)
-{
- return 0;
-}
-
} // namespace PowerISA
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 50ff73e..7f839d6 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -95,6 +95,8 @@
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
+ bool inUserMode() const override { return true; }
+
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index c2f4ac8..32cf046 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -157,12 +157,6 @@
inst->advancePC(pc);
}
-static inline bool
-inUserMode(ThreadContext *tc)
-{
- return true;
-}
-
} // namespace RiscvISA
#endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 21143dd..4fac56f 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -221,6 +221,14 @@
return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
}
+ bool
+ inUserMode() const override
+ {
+ PSTATE pstate = readMiscRegNoEffect(MISCREG_PSTATE);
+ HPSTATE hpstate = readMiscRegNoEffect(MISCREG_HPSTATE);
+ return !(pstate.priv || hpstate.hpriv);
+ }
+
typedef SparcISAParams Params;
const Params ¶ms() const;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 18b5164..8ec3e10 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,14 +50,6 @@
return ret;
}
-static inline bool
-inUserMode(ThreadContext *tc)
-{
- PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
- HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
- return !(pstate.priv || hpstate.hpriv);
-}
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 2cbce6e..f8327e8 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -104,6 +104,13 @@
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
+ bool
+ inUserMode() const override
+ {
+ HandyM5Reg m5reg = readMiscRegNoEffect(MISCREG_M5_REG);
+ return m5reg.cpl == 3;
+ }
+
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 1ff7b16..79274ca 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -53,17 +53,6 @@
return retPC;
}
- static inline bool
- inUserMode(ThreadContext *tc)
- {
- if (!FullSystem) {
- return true;
- } else {
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return m5reg.cpl == 3;
- }
- }
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 17c877e..2410b14 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -63,11 +63,11 @@
{
std::stringstream outs;
- if (!Debug::ExecUser || !Debug::ExecKernel) {
- bool in_user_mode = TheISA::inUserMode(thread);
- if (in_user_mode && !Debug::ExecUser) return;
- if (!in_user_mode && !Debug::ExecKernel) return;
- }
+ const bool in_user_mode = thread->getIsaPtr()->inUserMode();
+ if (in_user_mode && !Debug::ExecUser)
+ return;
+ if (!in_user_mode && !Debug::ExecKernel)
+ return;
if (Debug::ExecAsid)
outs << "A" << dec << thread->getIsaPtr()->getExecutingAsid()
<< " ";
@@ -78,7 +78,7 @@
Addr cur_pc = pc.instAddr();
Loader::SymbolTable::const_iterator it;
ccprintf(outs, "%#x", cur_pc);
- if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
+ if (Debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
(it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
Loader::debugSymbolTable.end()) {
Addr delta = cur_pc - it->address;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39323
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I624f9365124679343e988cabfb4e1929225b439a
Gerrit-Change-Number: 39323
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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