Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39336 )
Change subject: arch,cpu: Move TheISA::copyRegs to
TheISA::ISA::copyRegsFrom.
......................................................................
arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.
Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/linux/linux.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/utility.cc
M src/arch/power/SConscript
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/pagetable.hh
D src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/SConscript
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/linux/linux.hh
D src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/x86/linux/linux.hh
M src/arch/x86/utility.cc
M src/arch/x86/utility.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
32 files changed, 344 insertions(+), 440 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f4fabc1..db00b69 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -481,6 +481,52 @@
setupThreadContext();
}
+static void
+copyVecRegs(ThreadContext *src, ThreadContext *dest)
+{
+ auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
+
+ // The way vector registers are copied (VecReg vs VecElem) is relevant
+ // in the O3 model only.
+ if (src_mode == Enums::Full) {
+ for (auto idx = 0; idx < NumVecRegs; idx++)
+ dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
+ } else {
+ for (auto idx = 0; idx < NumVecRegs; idx++)
+ for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg;
elem_idx++)
+ dest->setVecElemFlat(
+ idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
+ }
+}
+
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ for (int i = 0; i < NumIntRegs; i++)
+ tc->setIntRegFlat(i, src->readIntRegFlat(i));
+
+ for (int i = 0; i < NumFloatRegs; i++)
+ tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
+
+ for (int i = 0; i < NumCCRegs; i++)
+ tc->setCCReg(i, src->readCCReg(i));
+
+ for (int i = 0; i < NumMiscRegs; i++)
+ tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+
+ copyVecRegs(src, tc);
+
+ // setMiscReg "with effect" will set the misc register mapping
correctly.
+ // e.g. updateRegMap(val)
+ tc->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
+
+ // Copy over the PC State
+ tc->pcState(src->pcState());
+
+ // Invalidate the tlb misc register cache
+ static_cast<MMU *>(tc->getMMUPtr())->invalidateMiscReg();
+}
+
RegVal
ISA::readMiscRegNoEffect(int misc_reg) const
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index d350378..ff885a8 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -900,6 +900,8 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
return ArmISA::inUserMode(cpsr);
}
+
+ void copyRegsFrom(ThreadContext *src) override;
};
}
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index ad773cd..9b824fc 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -57,7 +57,7 @@
ThreadContext *ptc, ThreadContext *ctc,
uint64_t stack, uint64_t tls)
{
- ArmISA::copyRegs(ptc, ctc);
+ ctc->getIsaPtr()->copyRegsFrom(ptc);
if (flags & TGT_CLONE_SETTLS) {
/* TPIDR_EL0 is architecturally mapped to TPIDRURW, so
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 31408f6..688ee8d 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -53,52 +53,6 @@
namespace ArmISA
{
-static void
-copyVecRegs(ThreadContext *src, ThreadContext *dest)
-{
- auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
-
- // The way vector registers are copied (VecReg vs VecElem) is relevant
- // in the O3 model only.
- if (src_mode == Enums::Full) {
- for (auto idx = 0; idx < NumVecRegs; idx++)
- dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
- } else {
- for (auto idx = 0; idx < NumVecRegs; idx++)
- for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg;
elem_idx++)
- dest->setVecElemFlat(
- idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
- }
-}
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- for (int i = 0; i < NumIntRegs; i++)
- dest->setIntRegFlat(i, src->readIntRegFlat(i));
-
- for (int i = 0; i < NumFloatRegs; i++)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
-
- for (int i = 0; i < NumCCRegs; i++)
- dest->setCCReg(i, src->readCCReg(i));
-
- for (int i = 0; i < NumMiscRegs; i++)
- dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-
- copyVecRegs(src, dest);
-
- // setMiscReg "with effect" will set the misc register mapping
correctly.
- // e.g. updateRegMap(val)
- dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
-
- // Copy over the PC State
- dest->pcState(src->pcState());
-
- // Invalidate the tlb misc register cache
- static_cast<MMU *>(dest->getMMUPtr())->invalidateMiscReg();
-}
-
void
sendEvent(ThreadContext *tc)
{
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 52c6ba0..621cd58 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -84,8 +84,6 @@
}
}
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
/** Send an event (SEV) to a specific PE if there isn't
* already a pending event */
void sendEvent(ThreadContext *tc);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 12c58ad..f5d2aa5 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -60,6 +60,8 @@
virtual uint64_t getExecutingAsid() const { return 0; }
virtual bool inUserMode() const = 0;
+
+ virtual void copyRegsFrom(ThreadContext *src) = 0;
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 81748c6..fe7cf69 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -158,6 +158,28 @@
}
}
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ // First loop through the integer registers.
+ for (int i = 0; i < NumIntRegs; i++)
+ tc->setIntRegFlat(i, src->readIntRegFlat(i));
+
+ // Then loop through the floating point registers.
+ for (int i = 0; i < NumFloatRegs; i++)
+ tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
+
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
+ // Copy misc. registers
+ for (int i = 0; i < NumMiscRegs; i++)
+ tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+
+ // Copy over the PC State
+ tc->pcState(src->pcState());
+}
+
void
ISA::configCP()
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 6242c62..ad7e6fc 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -162,6 +162,8 @@
return false;
}
}
+
+ void copyRegsFrom(ThreadContext *src) override;
};
}
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 7f98122..48154c1 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -206,26 +206,4 @@
}
}
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- // First loop through the integer registers.
- for (int i = 0; i < NumIntRegs; i++)
- dest->setIntRegFlat(i, src->readIntRegFlat(i));
-
- // Then loop through the floating point registers.
- for (int i = 0; i < NumFloatRegs; i++)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
-
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
- // Copy misc. registers
- for (int i = 0; i < NumMiscRegs; i++)
- dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-
- // Copy over the PC State
- dest->pcState(src->pcState());
-}
-
} // namespace MipsISA
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index cf79094..24bf5db 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -48,7 +48,6 @@
Source('remote_gdb.cc')
Source('se_workload.cc')
Source('tlb.cc')
- Source('utility.cc')
SimObject('PowerInterrupts.py')
SimObject('PowerISA.py')
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 02a04c2..df219e3 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -37,6 +37,7 @@
#include "arch/power/isa.hh"
+#include "cpu/thread_context.hh"
#include "params/PowerISA.hh"
namespace PowerISA
@@ -47,6 +48,26 @@
clear();
}
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ // First loop through the integer registers.
+ for (int i = 0; i < NumIntRegs; ++i)
+ tc->setIntReg(i, src->readIntReg(i));
+
+ // Then loop through the floating point registers.
+ for (int i = 0; i < NumFloatRegs; ++i)
+ tc->setFloatReg(i, src->readFloatReg(i));
+
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
+ //TODO Copy misc. registers
+
+ // Lastly copy PC/NPC
+ tc->pcState(src->pcState());
+}
+
const PowerISAParams &
ISA::params() const
{
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 0d00ec1..ea6a77a 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -134,6 +134,8 @@
return false;
}
+ void copyRegsFrom(ThreadContext *src) override;
+
const Params ¶ms() const;
ISA(const Params &p);
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index f4ec525..1f0ec4c 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -34,6 +34,7 @@
#include "arch/power/isa_traits.hh"
#include "arch/power/utility.hh"
+#include "sim/serialize.hh"
namespace PowerISA
{
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
deleted file mode 100644
index 9003b13..0000000
--- a/src/arch/power/utility.cc
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/power/utility.hh"
-
-#include "base/logging.hh"
-
-namespace PowerISA {
-
-void
-copyMiscRegs(ThreadContext *stc, ThreadContext *dest)
-{
-}
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- // First loop through the integer registers.
- for (int i = 0; i < NumIntRegs; ++i)
- dest->setIntReg(i, src->readIntReg(i));
-
- // Then loop through the floating point registers.
- for (int i = 0; i < NumFloatRegs; ++i)
- dest->setFloatReg(i, src->readFloatReg(i));
-
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
- // Copy misc. registers
- copyMiscRegs(src, dest);
-
- // Lastly copy PC/NPC
- dest->pcState(src->pcState());
-}
-
-} // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 13183f1..dfe3d06 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -31,15 +31,4 @@
#ifndef __ARCH_POWER_UTILITY_HH__
#define __ARCH_POWER_UTILITY_HH__
-#include "base/types.hh"
-#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-namespace PowerISA {
-
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace PowerISA
-
-
#endif // __ARCH_POWER_UTILITY_HH__
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 8401310..0eeee0c 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -182,6 +182,21 @@
clear();
}
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ // First loop through the integer registers.
+ for (int i = 0; i < NumIntRegs; ++i)
+ tc->setIntReg(i, src->readIntReg(i));
+
+ // Second loop through the float registers.
+ for (int i = 0; i < NumFloatRegs; ++i)
+ tc->setFloatReg(i, src->readFloatReg(i));
+
+ // Lastly copy PC/NPC
+ tc->pcState(src->pcState());
+}
+
const RiscvISAParams &
ISA::params() const
{
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 7f839d6..bce5568 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -97,6 +97,8 @@
bool inUserMode() const override { return true; }
+ void copyRegsFrom(ThreadContext *src) override;
+
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index 0b10b7a..124bd86 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -199,7 +199,7 @@
ThreadContext *ptc, ThreadContext *ctc,
uint64_t stack, uint64_t tls)
{
- RiscvISA::copyRegs(ptc, ctc);
+ ctc->getIsaPtr()->copyRegsFrom(ptc);
if (flags & TGT_CLONE_SETTLS)
ctc->setIntReg(RiscvISA::ThreadPointerReg, tls);
if (stack)
@@ -371,7 +371,7 @@
ThreadContext *ptc, ThreadContext *ctc,
uint64_t stack, uint64_t tls)
{
- RiscvISA::copyRegs(ptc, ctc);
+ ctc->getIsaPtr()->copyRegsFrom(ptc);
if (stack)
ctc->setIntReg(RiscvISA::StackPointerReg, stack);
}
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index f033b2b..5ff9fed 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -98,21 +98,6 @@
&& (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
}
-inline void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- // First loop through the integer registers.
- for (int i = 0; i < NumIntRegs; ++i)
- dest->setIntReg(i, src->readIntReg(i));
-
- // Second loop through the float registers.
- for (int i = 0; i < NumFloatRegs; ++i)
- dest->setFloatReg(i, src->readFloatReg(i));
-
- // Lastly copy PC/NPC
- dest->pcState(src->pcState());
-}
-
inline std::string
registerName(RegId reg)
{
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 5563702..0098781 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -45,7 +45,6 @@
Source('solaris/solaris.cc')
Source('tlb.cc')
Source('ua2005.cc')
- Source('utility.cc')
SimObject('SparcFsWorkload.py')
SimObject('SparcInterrupts.py')
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 20f4412..7e01e61 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -64,6 +64,186 @@
clear();
}
+static void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
+
+ // Read all the trap level dependent registers and save them off
+ for (int i = 1; i <= MaxTL; i++) {
+ src->setMiscRegNoEffect(MISCREG_TL, i);
+ dest->setMiscRegNoEffect(MISCREG_TL, i);
+
+ dest->setMiscRegNoEffect(MISCREG_TT,
+ src->readMiscRegNoEffect(MISCREG_TT));
+ dest->setMiscRegNoEffect(MISCREG_TPC,
+ src->readMiscRegNoEffect(MISCREG_TPC));
+ dest->setMiscRegNoEffect(MISCREG_TNPC,
+ src->readMiscRegNoEffect(MISCREG_TNPC));
+ dest->setMiscRegNoEffect(MISCREG_TSTATE,
+ src->readMiscRegNoEffect(MISCREG_TSTATE));
+ }
+
+ // Save off the traplevel
+ dest->setMiscRegNoEffect(MISCREG_TL, tl);
+ src->setMiscRegNoEffect(MISCREG_TL, tl);
+
+
+ // ASRs
+// dest->setMiscRegNoEffect(MISCREG_Y,
+// src->readMiscRegNoEffect(MISCREG_Y));
+// dest->setMiscRegNoEffect(MISCREG_CCR,
+// src->readMiscRegNoEffect(MISCREG_CCR));
+ dest->setMiscReg(MISCREG_ASI,
+ src->readMiscRegNoEffect(MISCREG_ASI));
+ dest->setMiscRegNoEffect(MISCREG_TICK,
+ src->readMiscRegNoEffect(MISCREG_TICK));
+ dest->setMiscRegNoEffect(MISCREG_FPRS,
+ src->readMiscRegNoEffect(MISCREG_FPRS));
+ dest->setMiscRegNoEffect(MISCREG_SOFTINT,
+ src->readMiscRegNoEffect(MISCREG_SOFTINT));
+ dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
+ src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
+ dest->setMiscRegNoEffect(MISCREG_STICK,
+ src->readMiscRegNoEffect(MISCREG_STICK));
+ dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
+ src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
+
+ // Priv Registers
+ dest->setMiscRegNoEffect(MISCREG_TICK,
+ src->readMiscRegNoEffect(MISCREG_TICK));
+ dest->setMiscRegNoEffect(MISCREG_TBA,
+ src->readMiscRegNoEffect(MISCREG_TBA));
+ dest->setMiscRegNoEffect(MISCREG_PSTATE,
+ src->readMiscRegNoEffect(MISCREG_PSTATE));
+ dest->setMiscRegNoEffect(MISCREG_PIL,
+ src->readMiscRegNoEffect(MISCREG_PIL));
+ dest->setMiscReg(MISCREG_CWP,
+ src->readMiscRegNoEffect(MISCREG_CWP));
+// dest->setMiscRegNoEffect(MISCREG_CANSAVE,
+// src->readMiscRegNoEffect(MISCREG_CANSAVE));
+// dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
+// src->readMiscRegNoEffect(MISCREG_CANRESTORE));
+// dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
+// src->readMiscRegNoEffect(MISCREG_OTHERWIN));
+// dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
+// src->readMiscRegNoEffect(MISCREG_CLEANWIN));
+// dest->setMiscRegNoEffect(MISCREG_WSTATE,
+// src->readMiscRegNoEffect(MISCREG_WSTATE));
+ dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
+
+ // Hyperprivilged registers
+ dest->setMiscRegNoEffect(MISCREG_HPSTATE,
+ src->readMiscRegNoEffect(MISCREG_HPSTATE));
+ dest->setMiscRegNoEffect(MISCREG_HINTP,
+ src->readMiscRegNoEffect(MISCREG_HINTP));
+ dest->setMiscRegNoEffect(MISCREG_HTBA,
+ src->readMiscRegNoEffect(MISCREG_HTBA));
+ dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+ src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+ dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
+ src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
+
+ // FSR
+ dest->setMiscRegNoEffect(MISCREG_FSR,
+ src->readMiscRegNoEffect(MISCREG_FSR));
+
+ // Strand Status Register
+ dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+ src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+
+ // MMU Registers
+ dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
+ src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
+ dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
+ src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
+ dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
+ src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
+ dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
+ src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
+
+ // Scratchpad Registers
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
+ dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
+ src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
+
+ // Queue Registers
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
+ dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
+ src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
+}
+
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ // First loop through the integer registers.
+ int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
+ int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
+ // Globals
+ for (int x = 0; x < MaxGL; ++x) {
+ src->setMiscReg(MISCREG_GL, x);
+ tc->setMiscReg(MISCREG_GL, x);
+ // Skip %g0 which is always zero.
+ for (int y = 1; y < 8; y++)
+ tc->setIntReg(y, src->readIntReg(y));
+ }
+ // Locals and ins. Outs are all also ins.
+ for (int x = 0; x < NWindows; ++x) {
+ src->setMiscReg(MISCREG_CWP, x);
+ tc->setMiscReg(MISCREG_CWP, x);
+ for (int y = 16; y < 32; y++)
+ tc->setIntReg(y, src->readIntReg(y));
+ }
+ // Microcode reg and pseudo int regs (misc regs in the integer
regfile).
+ for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
+ tc->setIntReg(y, src->readIntReg(y));
+
+ // Restore src's GL, CWP
+ src->setMiscReg(MISCREG_GL, old_gl);
+ src->setMiscReg(MISCREG_CWP, old_cwp);
+
+
+ // Then loop through the floating point registers.
+ for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
+ tc->setFloatReg(i, src->readFloatReg(i));
+ }
+
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
+ // Copy misc. registers
+ copyMiscRegs(src, tc);
+
+ // Lastly copy PC/NPC
+ tc->pcState(src->pcState());
+}
+
const SparcISAParams &
ISA::params() const
{
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 4fac56f..525a391 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -229,6 +229,8 @@
return !(pstate.priv || hpstate.hpriv);
}
+ void copyRegsFrom(ThreadContext *src) override;
+
typedef SparcISAParams Params;
const Params ¶ms() const;
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index 431ec06..649beea 100644
--- a/src/arch/sparc/linux/linux.hh
+++ b/src/arch/sparc/linux/linux.hh
@@ -29,7 +29,9 @@
#ifndef __ARCH_SPARC_LINUX_LINUX_HH__
#define __ARCH_SPARC_LINUX_LINUX_HH__
+#include "arch/sparc/asi.hh"
#include "arch/sparc/utility.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
class SparcLinux : public Linux
@@ -216,7 +218,7 @@
ThreadContext *ptc, ThreadContext *ctc,
uint64_t stack, uint64_t tls)
{
- SparcISA::copyRegs(ptc, ctc);
+ ctc->getIsaPtr()->copyRegsFrom(ptc);
ctc->setIntReg(SparcISA::INTREG_OTHERWIN, 0);
ctc->setIntReg(SparcISA::INTREG_CANRESTORE, 0);
ctc->setIntReg(SparcISA::INTREG_CANSAVE, SparcISA::NWindows - 2);
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
deleted file mode 100644
index a0c0f8b..0000000
--- a/src/arch/sparc/utility.cc
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/utility.hh"
-
-#include "arch/sparc/faults.hh"
-#include "mem/port_proxy.hh"
-
-namespace SparcISA
-{
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-
- uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
-
- // Read all the trap level dependent registers and save them off
- for (int i = 1; i <= MaxTL; i++) {
- src->setMiscRegNoEffect(MISCREG_TL, i);
- dest->setMiscRegNoEffect(MISCREG_TL, i);
-
- dest->setMiscRegNoEffect(MISCREG_TT,
- src->readMiscRegNoEffect(MISCREG_TT));
- dest->setMiscRegNoEffect(MISCREG_TPC,
- src->readMiscRegNoEffect(MISCREG_TPC));
- dest->setMiscRegNoEffect(MISCREG_TNPC,
- src->readMiscRegNoEffect(MISCREG_TNPC));
- dest->setMiscRegNoEffect(MISCREG_TSTATE,
- src->readMiscRegNoEffect(MISCREG_TSTATE));
- }
-
- // Save off the traplevel
- dest->setMiscRegNoEffect(MISCREG_TL, tl);
- src->setMiscRegNoEffect(MISCREG_TL, tl);
-
-
- // ASRs
-// dest->setMiscRegNoEffect(MISCREG_Y,
-// src->readMiscRegNoEffect(MISCREG_Y));
-// dest->setMiscRegNoEffect(MISCREG_CCR,
-// src->readMiscRegNoEffect(MISCREG_CCR));
- dest->setMiscReg(MISCREG_ASI,
- src->readMiscRegNoEffect(MISCREG_ASI));
- dest->setMiscRegNoEffect(MISCREG_TICK,
- src->readMiscRegNoEffect(MISCREG_TICK));
- dest->setMiscRegNoEffect(MISCREG_FPRS,
- src->readMiscRegNoEffect(MISCREG_FPRS));
- dest->setMiscRegNoEffect(MISCREG_SOFTINT,
- src->readMiscRegNoEffect(MISCREG_SOFTINT));
- dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
- src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
- dest->setMiscRegNoEffect(MISCREG_STICK,
- src->readMiscRegNoEffect(MISCREG_STICK));
- dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
- src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
-
- // Priv Registers
- dest->setMiscRegNoEffect(MISCREG_TICK,
- src->readMiscRegNoEffect(MISCREG_TICK));
- dest->setMiscRegNoEffect(MISCREG_TBA,
- src->readMiscRegNoEffect(MISCREG_TBA));
- dest->setMiscRegNoEffect(MISCREG_PSTATE,
- src->readMiscRegNoEffect(MISCREG_PSTATE));
- dest->setMiscRegNoEffect(MISCREG_PIL,
- src->readMiscRegNoEffect(MISCREG_PIL));
- dest->setMiscReg(MISCREG_CWP,
- src->readMiscRegNoEffect(MISCREG_CWP));
-// dest->setMiscRegNoEffect(MISCREG_CANSAVE,
-// src->readMiscRegNoEffect(MISCREG_CANSAVE));
-// dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
-// src->readMiscRegNoEffect(MISCREG_CANRESTORE));
-// dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
-// src->readMiscRegNoEffect(MISCREG_OTHERWIN));
-// dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
-// src->readMiscRegNoEffect(MISCREG_CLEANWIN));
-// dest->setMiscRegNoEffect(MISCREG_WSTATE,
-// src->readMiscRegNoEffect(MISCREG_WSTATE));
- dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
-
- // Hyperprivilged registers
- dest->setMiscRegNoEffect(MISCREG_HPSTATE,
- src->readMiscRegNoEffect(MISCREG_HPSTATE));
- dest->setMiscRegNoEffect(MISCREG_HINTP,
- src->readMiscRegNoEffect(MISCREG_HINTP));
- dest->setMiscRegNoEffect(MISCREG_HTBA,
- src->readMiscRegNoEffect(MISCREG_HTBA));
- dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
- src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
- dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
- src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
-
- // FSR
- dest->setMiscRegNoEffect(MISCREG_FSR,
- src->readMiscRegNoEffect(MISCREG_FSR));
-
- // Strand Status Register
- dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
- src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
-
- // MMU Registers
- dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
- src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
- dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
- src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
- dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
- src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
- dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
- src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
-
- // Scratchpad Registers
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
- dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
- src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
-
- // Queue Registers
- dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
- src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
- src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
- src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
- src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
- src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
- src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
- src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
- dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
- src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
-}
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- // First loop through the integer registers.
- int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
- int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
- // Globals
- for (int x = 0; x < MaxGL; ++x) {
- src->setMiscReg(MISCREG_GL, x);
- dest->setMiscReg(MISCREG_GL, x);
- // Skip %g0 which is always zero.
- for (int y = 1; y < 8; y++)
- dest->setIntReg(y, src->readIntReg(y));
- }
- // Locals and ins. Outs are all also ins.
- for (int x = 0; x < NWindows; ++x) {
- src->setMiscReg(MISCREG_CWP, x);
- dest->setMiscReg(MISCREG_CWP, x);
- for (int y = 16; y < 32; y++)
- dest->setIntReg(y, src->readIntReg(y));
- }
- // Microcode reg and pseudo int regs (misc regs in the integer
regfile).
- for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
- dest->setIntReg(y, src->readIntReg(y));
-
- // Restore src's GL, CWP
- src->setMiscReg(MISCREG_GL, old_gl);
- src->setMiscReg(MISCREG_CWP, old_cwp);
-
-
- // Then loop through the floating point registers.
- for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
- dest->setFloatReg(i, src->readFloatReg(i));
- }
-
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
- // Copy misc. registers
- copyMiscRegs(src, dest);
-
- // Lastly copy PC/NPC
- dest->pcState(src->pcState());
-}
-
-} // namespace SPARC_ISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 78e5e25..5c3d12d 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -29,20 +29,4 @@
#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/registers.hh"
-#include "arch/sparc/tlb.hh"
-#include "base/bitfield.hh"
-#include "base/logging.hh"
-#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-#include "sim/full_system.hh"
-
-namespace SparcISA
-{
-
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace SparcISA
-
#endif
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 2465a19..c6bab56 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -137,6 +137,42 @@
clear();
}
+static void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ // This function assumes no side effects other than TLB invalidation
+ // need to be considered while copying state. That will likely not be
+ // true in the future.
+ for (int i = 0; i < NUM_MISCREGS; ++i) {
+ if (!isValidMiscReg(i))
+ continue;
+
+ dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+ }
+
+ // The TSC has to be updated with side-effects if the CPUs in a
+ // CPU switch have different frequencies.
+ dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
+
+ dest->getMMUPtr()->flushAll();
+}
+
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+ //copy int regs
+ for (int i = 0; i < NumIntRegs; ++i)
+ tc->setIntRegFlat(i, src->readIntRegFlat(i));
+ //copy float regs
+ for (int i = 0; i < NumFloatRegs; ++i)
+ tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
+ //copy condition-code regs
+ for (int i = 0; i < NumCCRegs; ++i)
+ tc->setCCRegFlat(i, src->readCCRegFlat(i));
+ copyMiscRegs(src, tc);
+ tc->pcState(src->pcState());
+}
+
const X86ISAParams &
ISA::params() const
{
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index f8327e8..5ad9f7d 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -111,6 +111,8 @@
return m5reg.cpl == 3;
}
+ void copyRegsFrom(ThreadContext *src) override;
+
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index 697892c..6c98db8 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -54,7 +54,7 @@
ThreadContext *ptc, ThreadContext *ctc,
uint64_t stack, uint64_t tls)
{
- X86ISA::copyRegs(ptc, ctc);
+ ctc->getIsaPtr()->copyRegsFrom(ptc);
if (flags & TGT_CLONE_SETTLS) {
ctc->setMiscRegNoEffect(X86ISA::MISCREG_FS_BASE, tls);
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index c664620..5293d6b 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -49,42 +49,6 @@
namespace X86ISA
{
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
- // This function assumes no side effects other than TLB invalidation
- // need to be considered while copying state. That will likely not be
- // true in the future.
- for (int i = 0; i < NUM_MISCREGS; ++i) {
- if (!isValidMiscReg(i))
- continue;
-
- dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
- }
-
- // The TSC has to be updated with side-effects if the CPUs in a
- // CPU switch have different frequencies.
- dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
-
- dest->getMMUPtr()->flushAll();
-}
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- //copy int regs
- for (int i = 0; i < NumIntRegs; ++i)
- dest->setIntRegFlat(i, src->readIntRegFlat(i));
- //copy float regs
- for (int i = 0; i < NumFloatRegs; ++i)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
- //copy condition-code regs
- for (int i = 0; i < NumCCRegs; ++i)
- dest->setCCRegFlat(i, src->readCCRegFlat(i));
- copyMiscRegs(src, dest);
- dest->pcState(src->pcState());
-}
-
uint64_t
getRFlags(ThreadContext *tc)
{
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index a572637..0c0b1c0 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -44,8 +44,6 @@
namespace X86ISA
{
- void copyRegs(ThreadContext *src, ThreadContext *dest);
-
/**
* Reconstruct the rflags register from the internal gem5 register
* state.
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index bea4dc7..d0abec7 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -155,7 +155,7 @@
// Prevent squashing
thread->noSquashFromTC = true;
- TheISA::copyRegs(tc, this);
+ getIsaPtr()->copyRegsFrom(tc);
thread->noSquashFromTC = false;
if (!FullSystem)
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 8a54076..0604388 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -170,7 +170,7 @@
void
SimpleThread::copyArchRegs(ThreadContext *src_tc)
{
- TheISA::copyRegs(src_tc, this);
+ getIsaPtr()->copyRegsFrom(src_tc);
}
// hardware transactional memory
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Gerrit-Change-Number: 39336
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