Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39561 )
Change subject: arch-arm: Stop "using namespace std"
......................................................................
arch-arm: Stop "using namespace std"
Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39561
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/mem.cc
M src/arch/arm/insts/mem64.cc
M src/arch/arm/linux/process.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/pauth_helpers.cc
M src/arch/arm/process.cc
M src/arch/arm/qarma.cc
M src/arch/arm/remote_gdb.cc
M src/arch/arm/self_debug.cc
M src/arch/arm/system.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
13 files changed, 45 insertions(+), 60 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 1ce9705..e20aef9 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -45,7 +45,6 @@
#include "arch/arm/generated/decoder.hh"
#include "arch/arm/insts/neon64_mem.hh"
-using namespace std;
using namespace ArmISAInst;
namespace ArmISA
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index e44fc96..8ee3f49 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -42,8 +42,6 @@
#include "base/loader/symtab.hh"
-using namespace std;
-
namespace ArmISA
{
@@ -75,10 +73,10 @@
}
}
-string
+std::string
RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)
const
{
- stringstream ss;
+ std::stringstream ss;
switch (mode) {
case DecrementAfter:
printMnemonic(ss, "da");
@@ -100,10 +98,10 @@
return ss.str();
}
-string
+std::string
SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)
const
{
- stringstream ss;
+ std::stringstream ss;
switch (mode) {
case DecrementAfter:
printMnemonic(ss, "da");
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index ed159be..44fe735 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -41,8 +41,6 @@
#include "base/loader/symtab.hh"
#include "mem/request.hh"
-using namespace std;
-
namespace ArmISA
{
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 7f86c24..cba3d14 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -54,7 +54,6 @@
#include "sim/syscall_emul.hh"
#include "sim/system.hh"
-using namespace std;
using namespace ArmISA;
const Addr ArmLinuxProcess32::commPage = 0xffff0000;
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index b5af9b6..5dfbd48 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -333,8 +333,6 @@
return MISCREG_CP14_UNIMPL;
}
-using namespace std;
-
MiscRegIndex
decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
{
@@ -3393,7 +3391,7 @@
return MISCREG_UNKNOWN;
}
-bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
+std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized
below
void
ISA::initializeMiscRegMetadata()
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 7424eb3..aa93384 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -41,7 +41,6 @@
#include "base/bitfield.hh"
using namespace ArmISA;
-using namespace std;
bool
ArmISA::calculateTBI(ThreadContext* tc, ExceptionLevel el,
@@ -101,11 +100,11 @@
using64k = el == EL2 ? tcr2.tg0 == 0x1 : tcr3.tg0 == 0x1 ;
}
uint32_t max_limit_tsz_field = using64k ? 47 : 48;
- tsz_field = min(tsz_field, max_limit_tsz_field);
+ tsz_field = std::min(tsz_field, max_limit_tsz_field);
const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
uint32_t tszmin = (using64k && (bool)mm_fr2.varange) ? 12 : 16;
- tsz_field = max(tsz_field, tszmin);
+ tsz_field = std::max(tsz_field, tszmin);
return (64-tsz_field);
}
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6f37d11..86bc8e2 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -55,7 +55,6 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
-using namespace std;
using namespace ArmISA;
ArmProcess::ArmProcess(const ProcessParams ¶ms,
@@ -78,9 +77,9 @@
Addr next_thread_stack_base = stack_base - max_stack_size;
Addr mmap_end = 0x40000000L;
- memState = make_shared<MemState>(this, brk_point, stack_base,
- max_stack_size,
next_thread_stack_base,
- mmap_end);
+ memState = std::make_shared<MemState>(
+ this, brk_point, stack_base, max_stack_size,
+ next_thread_stack_base, mmap_end);
}
ArmProcess64::ArmProcess64(
@@ -94,9 +93,9 @@
Addr next_thread_stack_base = stack_base - max_stack_size;
Addr mmap_end = 0x4000000000L;
- memState = make_shared<MemState>(this, brk_point, stack_base,
- max_stack_size,
next_thread_stack_base,
- mmap_end);
+ memState = std::make_shared<MemState>(
+ this, brk_point, stack_base, max_stack_size,
+ next_thread_stack_base, mmap_end);
}
void
@@ -257,7 +256,7 @@
std::vector<AuxVector<IntType>> auxv;
- string filename;
+ std::string filename;
if (argv.size() < 1)
filename = "";
else
@@ -318,7 +317,7 @@
// A sentry NULL void pointer at the top of the stack.
int sentry_size = intSize;
- string platform = "v71";
+ std::string platform = "v71";
int platform_size = platform.size() + 1;
// Bytes for AT_RANDOM above, we'll just keep them 0
diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc
index 4e18b7d..5805709 100644
--- a/src/arch/arm/qarma.cc
+++ b/src/arch/arm/qarma.cc
@@ -42,7 +42,6 @@
#include "base/bitfield.hh"
using namespace QARMA;
-using namespace std;
uint8_t
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 4d4915b..96344a9 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -163,7 +163,6 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
-using namespace std;
using namespace ArmISA;
static bool
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index e55df64..86e4ae5 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -42,7 +42,6 @@
#include "base/bitfield.hh"
using namespace ArmISA;
-using namespace std;
Fault
SelfDebug::testDebug(ThreadContext *tc, const RequestPtr &req,
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index bda5ed2..7f5fa13 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -51,7 +51,6 @@
#include "dev/arm/gic_v2.hh"
#include "mem/physical.hh"
-using namespace std;
using namespace Linux;
using namespace ArmISA;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 91c7088..6f16f6c 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -71,7 +71,6 @@
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
-using namespace std;
using namespace ArmISA;
TLB::TLB(const ArmTLBParams &p)
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index cdb24ca..6521b27 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -54,7 +54,6 @@
#include "sim/faults.hh"
#include "sim/sim_exit.hh"
-using namespace std;
using namespace ArmISA;
namespace Trace {
@@ -68,7 +67,8 @@
TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord;
TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType;
-list<TarmacParserRecord::ParserRegEntry>
TarmacParserRecord::destRegRecords;
+std::list<TarmacParserRecord::ParserRegEntry>
+ TarmacParserRecord::destRegRecords;
char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength];
TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
@@ -737,10 +737,10 @@
void
TarmacParserRecord::TarmacParserRecordEvent::process()
{
- ostream &outs = Trace::output();
+ std::ostream &outs = Trace::output();
- list<ParserRegEntry>::iterator it = destRegRecords.begin(),
- end = destRegRecords.end();
+ std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
+ end = destRegRecords.end();
std::vector<uint64_t> values;
@@ -915,14 +915,14 @@
TarmacParserRecord::printMismatchHeader(inst, pc);
mismatch = true;
}
- outs << "diff> [" << it->repr << "] gem5: 0x" << hex;
+ outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex;
for (auto v : values)
- outs << setw(16) << setfill('0') << v;
+ outs << std::setw(16) << std::setfill('0') << v;
- outs << ", TARMAC: 0x" << hex;
+ outs << ", TARMAC: 0x" << std::hex;
for (auto v : it->values)
- outs << setw(16) << setfill('0') << v;
- outs << endl;
+ outs << std::setw(16) << std::setfill('0') << v;
+ outs << std::endl;
}
}
destRegRecords.clear();
@@ -947,14 +947,14 @@
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
ArmISA::PCState pc)
{
- ostream &outs = Trace::output();
- outs << "\nMismatch between gem5 and TARMAC trace @ " << dec <<
curTick()
- << " ticks\n"
- << "[seq_num: " << dec << instRecord.seq_num
- << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff)
+ std::ostream &outs = Trace::output();
+ outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
+ << curTick() << " ticks\n"
+ << "[seq_num: " << std::dec << instRecord.seq_num
+ << ", opcode: 0x" << std::hex << (staticInst->machInst &
0xffffffff)
<< ", PC: 0x" << pc.pc()
<< ", disasm: " << staticInst->disassemble(pc.pc()) << "]"
- << endl;
+ << std::endl;
}
TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
@@ -976,7 +976,7 @@
void
TarmacParserRecord::dump()
{
- ostream &outs = Trace::output();
+ std::ostream &outs = Trace::output();
uint64_t written_data = 0;
unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned;
@@ -1005,8 +1005,8 @@
if (pc.instAddr() != instRecord.addr) {
if (!mismatch)
printMismatchHeader(staticInst, pc);
- outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr()
- << ", TARMAC: 0x" << instRecord.addr << endl;
+ outs << "diff> [PC] gem5: 0x" << std::hex <<
pc.instAddr()
+ << ", TARMAC: 0x" << instRecord.addr << std::endl;
mismatch = true;
mismatchOnPcOrOpcode = true;
}
@@ -1014,9 +1014,9 @@
if (arm_inst->encoding() != instRecord.opcode) {
if (!mismatch)
printMismatchHeader(staticInst, pc);
- outs << "diff> [opcode] gem5: 0x" << hex
+ outs << "diff> [opcode] gem5: 0x" << std::hex
<< arm_inst->encoding()
- << ", TARMAC: 0x" << instRecord.opcode << endl;
+ << ", TARMAC: 0x" << instRecord.opcode <<
std::endl;
mismatch = true;
mismatchOnPcOrOpcode = true;
}
@@ -1049,10 +1049,10 @@
if (written_data != memRecord.data) {
if (!mismatch)
printMismatchHeader(staticInst, pc);
- outs << "diff> [mem(0x" << hex << memRecord.addr
+ outs << "diff> [mem(0x" << std::hex << memRecord.addr
<< ")] gem5: 0x" << written_data
<< ", TARMAC: 0x" << memRecord.data
- << endl;
+ << std::endl;
}
break;
@@ -1083,8 +1083,8 @@
bool
TarmacParserRecord::advanceTrace()
{
- ifstream& trace = parent.trace;
- trace >> hex; // All integer values are in hex base
+ std::ifstream& trace = parent.trace;
+ trace >> std::hex; // All integer values are in hex base
if (buf[0] != 'I') {
trace >> buf;
@@ -1201,9 +1201,9 @@
regRecord.index = miscRegMap[buf];
} else {
// Try match with upper case name (misc. register)
- string reg_name = buf;
- transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
- ::tolower);
+ std::string reg_name = buf;
+ std::transform(reg_name.begin(), reg_name.end(),
reg_name.begin(),
+ ::tolower);
if (miscRegMap.count(reg_name.c_str())) {
regRecord.type = REG_MISC;
regRecord.index = miscRegMap[reg_name.c_str()];
@@ -1327,7 +1327,7 @@
Addr pc;
int saved_offset;
- trace >> hex; // All integer values are in hex base
+ trace >> std::hex; // All integer values are in hex base
while (true) {
saved_offset = trace.tellg();
@@ -1338,7 +1338,7 @@
trace >> buf >> pc;
if (pc == startPc) {
// Set file pointer to the beginning of this line
- trace.seekg(saved_offset, ios::beg);
+ trace.seekg(saved_offset, std::ios::beg);
return;
} else {
trace.ignore(TarmacParserRecord::MaxLineLength, '\n');
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39561
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
Gerrit-Change-Number: 39561
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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