Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39702 )
Change subject: arch-arm: Fix CPTR_EL2 writes
......................................................................
arch-arm: Fix CPTR_EL2 writes
If E2H==1, CPTR_EL2.ZEN bits are not RES0.
Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f4fabc1..07b85a4 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -930,6 +930,7 @@
break;
case MISCREG_CPTR_EL2:
{
+ const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
const uint32_t ones = (uint32_t)(-1);
CPTR cptrMask = 0;
cptrMask.tcpac = ones;
@@ -937,6 +938,8 @@
cptrMask.tfp = ones;
if (haveSVE) {
cptrMask.tz = ones;
+ if (hcr.e2h)
+ cptrMask.zen = ones;
}
newVal &= cptrMask;
cptrMask = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Gerrit-Change-Number: 39702
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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