Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39318 )
Change subject: riscv: Export the system call ABI for use in gem5 ops.
......................................................................
riscv: Export the system call ABI for use in gem5 ops.
This ABI is effectively used by both the gem5 ops and system calls, in
system calls because it only relies on registers, and in gem5 ops by
inheritance.
Even though these ABIs happen to be the same and were initially defined
to be the same, this change creates a root "reg" ABI which will act as a
root for both so that there isn't an implication that changes to one
should be changes to both.
Change-Id: I8726d8628503be2ad7616a71cc48b66f13e7d955
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39318
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Ayaz Akram <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/SConscript
M src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
R src/arch/riscv/reg_abi.cc
C src/arch/riscv/reg_abi.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/se_workload.hh
7 files changed, 23 insertions(+), 22 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve
Ayaz Akram: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 0179fbc..472264f 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -51,8 +51,8 @@
Source('process.cc')
Source('pagetable.cc')
Source('pagetable_walker.cc')
+ Source('reg_abi.cc')
Source('remote_gdb.cc')
- Source('se_workload.cc')
Source('tlb.cc')
Source('linux/se_workload.cc')
diff --git a/src/arch/riscv/isa/formats/m5ops.isa
b/src/arch/riscv/isa/formats/m5ops.isa
index 11834f6..986438b 100644
--- a/src/arch/riscv/isa/formats/m5ops.isa
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -36,12 +36,11 @@
def format M5Op() {{
- iop = InstObjParams(name, Name, 'PseudoOp',
- 'uint64_t result;\n'
- 'PseudoInst::pseudoInst<PseudoInstABI>('
- 'xc->tcBase(), M5FUNC, result);\n'
- 'a0 = result',
- ['IsNonSpeculative', 'IsSerializeAfter'])
+ iop = InstObjParams(name, Name, 'PseudoOp', '''
+ uint64_t result;
+ PseudoInst::pseudoInst<RegABI64>(xc->tcBase(), M5FUNC, result);
+ a0 = result''',
+ ['IsNonSpeculative', 'IsSerializeAfter'])
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index d77d68e..799559a 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -81,6 +81,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/riscv/faults.hh"
#include "arch/riscv/mmu.hh"
+#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/registers.hh"
#include "arch/riscv/utility.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/reg_abi.cc
similarity index 91%
rename from src/arch/riscv/se_workload.cc
rename to src/arch/riscv/reg_abi.cc
index ce4679c..25aee6f 100644
--- a/src/arch/riscv/se_workload.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -25,13 +25,11 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/riscv/se_workload.hh"
+#include "arch/riscv/reg_abi.hh"
namespace RiscvISA
{
-const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
- 10, 11, 12, 13, 14, 15, 16
-};
+const std::vector<int> RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15,
16};
} // namespace RiscvISA
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/reg_abi.hh
similarity index 82%
copy from src/arch/riscv/se_workload.cc
copy to src/arch/riscv/reg_abi.hh
index ce4679c..492c117 100644
--- a/src/arch/riscv/se_workload.cc
+++ b/src/arch/riscv/reg_abi.hh
@@ -25,13 +25,22 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/riscv/se_workload.hh"
+#ifndef __ARCH_RISCV_REG_ABI_HH__
+#define __ARCH_RISCV_REG_ABI_HH__
+
+#include <vector>
+
+#include "sim/syscall_abi.hh"
namespace RiscvISA
{
-const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
- 10, 11, 12, 13, 14, 15, 16
+//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
+struct RegABI64 : public GenericSyscallABI64
+{
+ static const std::vector<int> ArgumentRegs;
};
} // namespace RiscvISA
+
+#endif // __ARCH_RISCV_REG_ABI_HH__
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 84a1924..9721635 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,11 +93,8 @@
const int ZeroReg = 0;
const int ReturnAddrReg = 1;
const int StackPointerReg = 2;
-const int GlobalPointerReg = 3;
const int ThreadPointerReg = 4;
-const int FramePointerReg = 8;
const int ReturnValueReg = 10;
-const std::vector<int> ReturnValueRegs = {10, 11};
const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index e0be5a1..d6df19c 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -28,11 +28,11 @@
#ifndef __ARCH_RISCV_SE_WORKLOAD_HH__
#define __ARCH_RISCV_SE_WORKLOAD_HH__
+#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/registers.hh"
#include "params/RiscvSEWorkload.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
-#include "sim/syscall_desc.hh"
namespace RiscvISA
{
@@ -53,10 +53,7 @@
::Loader::Arch getArch() const override { return ::Loader::Riscv64; }
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
- struct SyscallABI : public GenericSyscallABI64
- {
- static const std::vector<int> ArgumentRegs;
- };
+ using SyscallABI = RegABI64;
};
} // namespace RiscvISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8726d8628503be2ad7616a71cc48b66f13e7d955
Gerrit-Change-Number: 39318
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Ayaz Akram <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Peter Yuen <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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