Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39758 )
Change subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code
......................................................................
arch, mem, cpu, systemc: Remove Python 2.7 glue code
Remove uses of six and from __future__ imports as they are no longer
needed.
Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/fastmodel/SConscript
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/qos/QoSPolicy.py
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/systemc/tests/config.py
M src/systemc/tests/verify.py
M src/unittest/genini.py
17 files changed, 10 insertions(+), 48 deletions(-)
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index f5516fa..21b3d3c 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -35,7 +35,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
from itertools import cycle
Import('*')
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index 53026c1..0305a02 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -24,8 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import os
import sys
import re
diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index e34e06e..8bab7b9 100755
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -24,8 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop,
Rom
class Bah(object):
diff --git a/src/arch/x86/isa/microops/fpop.isa
b/src/arch/x86/isa/microops/fpop.isa
index 238fa93..346f0d6 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -105,8 +105,6 @@
let {{
- import six
-
# Make these empty strings so that concatenating onto
# them will always work.
header_output = ""
@@ -199,8 +197,7 @@
return cls
- @six.add_metaclass(FpOpMeta)
- class FpUnaryOp(X86Microop):
+ class FpUnaryOp(X86Microop, metaclass=FpOpMeta):
# This class itself doesn't act as a microop
abstract = True
@@ -235,8 +232,7 @@
"dataSize" : self.dataSize,
"spm" : self.spm}
- @six.add_metaclass(FpOpMeta)
- class FpBinaryOp(X86Microop):
+ class FpBinaryOp(X86Microop, metaclass=FpOpMeta):
# This class itself doesn't act as a microop
abstract = True
diff --git a/src/arch/x86/isa/microops/limmop.isa
b/src/arch/x86/isa/microops/limmop.isa
index b46be03..51310b4 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -106,16 +106,12 @@
}};
let {{
- import six
- if six.PY3:
- long = int
-
class LimmOp(X86Microop):
def __init__(self, dest, imm, dataSize="env.dataSize"):
self.className = "Limm"
self.mnemonic = "limm"
self.dest = dest
- if isinstance(imm, (int, long)):
+ if isinstance(imm, int):
imm = "ULL(%d)" % imm
self.imm = imm
self.dataSize = dataSize
@@ -145,7 +141,7 @@
self.className = "Lfpimm"
self.mnemonic = "lfpimm"
self.dest = dest
- if isinstance(imm, (int, long)):
+ if isinstance(imm, int):
imm = "ULL(%d)" % imm
elif isinstance(imm, float):
imm = "floatToBits64(%.16f)" % imm
diff --git a/src/arch/x86/isa/microops/mediaop.isa
b/src/arch/x86/isa/microops/mediaop.isa
index 7e5fd10..e149d44 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -202,8 +202,7 @@
return cls
- @six.add_metaclass(MediaOpMeta)
- class MediaOp(X86Microop):
+ class MediaOp(X86Microop, metaclass=MediaOpMeta):
# This class itself doesn't act as a microop
abstract = True
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index da1f9ae..c465dcc 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -416,8 +416,7 @@
return cls
- @six.add_metaclass(RegOpMeta)
- class RegOp(X86Microop):
+ class RegOp(X86Microop, metaclass=RegOpMeta):
# This class itself doesn't act as a microop
abstract = True
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 025e985..cb43419 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -38,8 +38,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import sys
from m5.SimObject import *
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index 1329dfb..e9003bd 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -36,8 +36,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 1118775..6f48c2b 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -36,8 +36,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
diff --git a/src/cpu/simple/BaseSimpleCPU.py
b/src/cpu/simple/BaseSimpleCPU.py
index f60d005..3da462c 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -24,8 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
from m5.defines import buildEnv
from m5.params import *
diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py
index 0945cd7..6e9e90e 100644
--- a/src/mem/qos/QoSPolicy.py
+++ b/src/mem/qos/QoSPolicy.py
@@ -33,8 +33,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from six import string_types
-
from m5.SimObject import *
from m5.params import *
@@ -78,7 +76,7 @@
for prio in self._requestor_priorities:
request_port = prio[0]
priority = prio[1]
- if isinstance(request_port, string_types):
+ if isinstance(request_port, str):
self.getCCObject().initRequestorName(
request_port, int(priority))
else:
@@ -115,7 +113,7 @@
for prio in self._requestor_scores:
request_port = prio[0]
score = prio[1]
- if isinstance(request_port, string_types):
+ if isinstance(request_port, str):
self.getCCObject().initRequestorName(
request_port, float(score))
else:
diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py
index f7f0494..c3afd2e 100644
--- a/src/mem/slicc/main.py
+++ b/src/mem/slicc/main.py
@@ -25,8 +25,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import os
import sys
diff --git a/src/mem/slicc/util.py b/src/mem/slicc/util.py
index 7afa4f8..ace879e 100644
--- a/src/mem/slicc/util.py
+++ b/src/mem/slicc/util.py
@@ -24,9 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-from six import string_types
-
import os
import sys
@@ -50,7 +47,7 @@
class Location(object):
def __init__(self, filename, lineno, no_warning=False):
- if not isinstance(filename, string_types):
+ if not isinstance(filename, str):
raise AttributeError(
"filename must be a string, found
{}".format(type(filename)))
if not isinstance(lineno, int):
diff --git a/src/systemc/tests/config.py b/src/systemc/tests/config.py
index f7af1a5..b199080 100755
--- a/src/systemc/tests/config.py
+++ b/src/systemc/tests/config.py
@@ -23,8 +23,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import argparse
import m5
import os
diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py
index 2c0ebc9..6b4cf5c 100755
--- a/src/systemc/tests/verify.py
+++ b/src/systemc/tests/verify.py
@@ -25,8 +25,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import argparse
import collections
import difflib
@@ -38,7 +36,6 @@
import os
import re
import subprocess
-import six
import sys
script_path = os.path.abspath(inspect.getfile(inspect.currentframe()))
@@ -110,8 +107,7 @@
super(TestPhaseMeta, cls).__init__(name, bases, d)
-@six.add_metaclass(TestPhaseMeta)
-class TestPhaseBase(object):
+class TestPhaseBase(object, metaclass=TestPhaseMeta):
abstract = True
def __init__(self, main_args, *args):
diff --git a/src/unittest/genini.py b/src/unittest/genini.py
index 2575fc0..854ce02 100755
--- a/src/unittest/genini.py
+++ b/src/unittest/genini.py
@@ -25,8 +25,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import getopt, os, os.path, sys
from os.path import join as joinpath, realpath
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Gerrit-Change-Number: 39758
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-MessageType: newchange
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