Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39655 )
Change subject: base,cpu,sim: Stop "using namespace TheISA".
......................................................................
base,cpu,sim: Stop "using namespace TheISA".
This was mostly not used to begin with, but also when it was used, it
would obscure places where there were types, functions, etc, which were
switched between ISAs at compile time, and which would need to be
cleaned up to allow more than one ISA at a time.
Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39655
Reviewed-by: Bobby R. Bruce <[email protected]>
Reviewed-by: Daniel Carvalho <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/base/remote_gdb.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu_impl.hh
M src/cpu/exetrace.cc
M src/cpu/inteltrace.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
M src/cpu/thread_context.cc
M src/sim/process.cc
M src/sim/syscall_emul.cc
M src/sim/system.cc
14 files changed, 43 insertions(+), 71 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 0c1215e..1e86a69 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -151,8 +151,6 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
static const char GDBStart = '$';
static const char GDBEnd = '#';
static const char GDBGoodP = '+';
@@ -803,7 +801,7 @@
bool
BaseRemoteGDB::checkBpLen(size_t len)
{
- return len == sizeof(MachInst);
+ return len == sizeof(TheISA::MachInst);
}
bool
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 8815530..a9baf88 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,8 +52,6 @@
#include "params/CheckerCPU.hh"
#include "sim/full_system.hh"
-using namespace TheISA;
-
void
CheckerCPU::init()
{
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 733cf1c..7fe05c6 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -59,8 +59,6 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-using namespace TheISA;
-
template <class Impl>
void
Checker<Impl>::advancePC(const Fault &fault)
@@ -200,7 +198,7 @@
Fault fault = NoFault;
// maintain $r0 semantics
- thread->setIntReg(ZeroReg, 0);
+ thread->setIntReg(TheISA::ZeroReg, 0);
// Check if any recent PC changes match up with anything we
// expect to happen. This is mostly to check if traps or
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 02ede1a..7bf60e7 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -53,8 +53,6 @@
#include "debug/FmtTicksOff.hh"
#include "enums/OpClass.hh"
-using namespace TheISA;
-
namespace Trace {
void
@@ -77,7 +75,7 @@
Addr cur_pc = pc.instAddr();
Loader::SymbolTable::const_iterator it;
ccprintf(outs, "%#x", cur_pc);
- if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
+ if (Debug::ExecSymbol && (!FullSystem || !TheISA::inUserMode(thread))
&&
(it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
Loader::debugSymbolTable.end()) {
Addr delta = cur_pc - it->address;
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 4e36a9d..2212dbf 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -34,8 +34,6 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
-using namespace TheISA;
-
namespace Trace {
void
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 56cf46c..c84f89b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -64,8 +64,6 @@
struct BaseCPUParams;
-using namespace TheISA;
-
BaseO3CPU::BaseO3CPU(const BaseCPUParams ¶ms)
: BaseCPU(params)
{
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2c6a16c..d811480 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -610,7 +610,6 @@
Fault
LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
{
- using namespace TheISA;
// Execute a specific load.
Fault load_fault = NoFault;
@@ -678,7 +677,6 @@
Fault
LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst)
{
- using namespace TheISA;
// Make sure that a store exists.
assert(stores != 0);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ae4ffec..f0c276b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -58,8 +58,6 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
void
AtomicSimpleCPU::init()
{
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 113f8e6..62df848 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -77,8 +77,6 @@
#include "sim/stats.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
: BaseCPU(p),
curThread(0),
@@ -298,7 +296,7 @@
// set up memory request for instruction fetch
DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr,
fetchPC);
- req->setVirt(fetchPC, sizeof(MachInst), Request::INST_FETCH,
+ req->setVirt(fetchPC, sizeof(TheISA::MachInst), Request::INST_FETCH,
instRequestorId(), instAddr);
}
@@ -310,7 +308,7 @@
SimpleThread* thread = t_info.thread;
// maintain $r0 semantics
- thread->setIntReg(ZeroReg, 0);
+ thread->setIntReg(TheISA::ZeroReg, 0);
// resets predicates
t_info.setPredicate(true);
@@ -348,7 +346,7 @@
thread->pcState(pcState);
} else {
t_info.stayAtPC = true;
- t_info.fetchOffset += sizeof(MachInst);
+ t_info.fetchOffset += sizeof(TheISA::MachInst);
}
//If we decoded an instruction and it's microcoded, start pulling
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index aaabda5..3109f8a 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -58,8 +58,6 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
void
TimingSimpleCPU::init()
{
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index d1d89df..16db818 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -141,37 +141,36 @@
void
serialize(const ThreadContext &tc, CheckpointOut &cp)
{
- using namespace TheISA;
-
- RegVal floatRegs[NumFloatRegs];
- for (int i = 0; i < NumFloatRegs; ++i)
+ RegVal floatRegs[TheISA::NumFloatRegs];
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i)
floatRegs[i] = tc.readFloatRegFlat(i);
// This is a bit ugly, but needed to maintain backwards
// compatibility.
- arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
+ arrayParamOut(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs);
- std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
- for (int i = 0; i < NumVecRegs; ++i) {
+ std::vector<TheISA::VecRegContainer> vecRegs(TheISA::NumVecRegs);
+ for (int i = 0; i < TheISA::NumVecRegs; ++i) {
vecRegs[i] = tc.readVecRegFlat(i);
}
SERIALIZE_CONTAINER(vecRegs);
- std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
- for (int i = 0; i < NumVecPredRegs; ++i) {
+ std::vector<TheISA::VecPredRegContainer>
+ vecPredRegs(TheISA::NumVecPredRegs);
+ for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
vecPredRegs[i] = tc.readVecPredRegFlat(i);
}
SERIALIZE_CONTAINER(vecPredRegs);
- RegVal intRegs[NumIntRegs];
- for (int i = 0; i < NumIntRegs; ++i)
+ RegVal intRegs[TheISA::NumIntRegs];
+ for (int i = 0; i < TheISA::NumIntRegs; ++i)
intRegs[i] = tc.readIntRegFlat(i);
- SERIALIZE_ARRAY(intRegs, NumIntRegs);
+ SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
- if (NumCCRegs) {
- RegVal ccRegs[NumCCRegs];
- for (int i = 0; i < NumCCRegs; ++i)
+ if (TheISA::NumCCRegs) {
+ RegVal ccRegs[TheISA::NumCCRegs];
+ for (int i = 0; i < TheISA::NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
- SERIALIZE_ARRAY(ccRegs, NumCCRegs);
+ SERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs);
}
tc.pcState().serialize(cp);
@@ -182,40 +181,39 @@
void
unserialize(ThreadContext &tc, CheckpointIn &cp)
{
- using namespace TheISA;
-
- RegVal floatRegs[NumFloatRegs];
+ RegVal floatRegs[TheISA::NumFloatRegs];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
- arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
- for (int i = 0; i < NumFloatRegs; ++i)
+ arrayParamIn(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs);
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i)
tc.setFloatRegFlat(i, floatRegs[i]);
- std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
+ std::vector<TheISA::VecRegContainer> vecRegs(TheISA::NumVecRegs);
UNSERIALIZE_CONTAINER(vecRegs);
- for (int i = 0; i < NumVecRegs; ++i) {
+ for (int i = 0; i < TheISA::NumVecRegs; ++i) {
tc.setVecRegFlat(i, vecRegs[i]);
}
- std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
+ std::vector<TheISA::VecPredRegContainer>
+ vecPredRegs(TheISA::NumVecPredRegs);
UNSERIALIZE_CONTAINER(vecPredRegs);
- for (int i = 0; i < NumVecPredRegs; ++i) {
+ for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
tc.setVecPredRegFlat(i, vecPredRegs[i]);
}
- RegVal intRegs[NumIntRegs];
- UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
- for (int i = 0; i < NumIntRegs; ++i)
+ RegVal intRegs[TheISA::NumIntRegs];
+ UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+ for (int i = 0; i < TheISA::NumIntRegs; ++i)
tc.setIntRegFlat(i, intRegs[i]);
- if (NumCCRegs) {
- RegVal ccRegs[NumCCRegs];
- UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
- for (int i = 0; i < NumCCRegs; ++i)
+ if (TheISA::NumCCRegs) {
+ RegVal ccRegs[TheISA::NumCCRegs];
+ UNSERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs);
+ for (int i = 0; i < TheISA::NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);
}
- PCState pcState;
+ TheISA::PCState pcState;
pcState.unserialize(cp);
tc.pcState(pcState);
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 1ae8d40..21d4c2a 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -67,8 +67,6 @@
#include "sim/syscall_desc.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
namespace
{
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index c85d893..8f04cd5 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -53,8 +53,6 @@
#include "sim/syscall_desc.hh"
#include "sim/system.hh"
-using namespace TheISA;
-
void
warnUnsupportedOS(std::string syscall_name)
{
diff --git a/src/sim/system.cc b/src/sim/system.cc
index f2f10bc..bb3c0be 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -71,8 +71,6 @@
#include "sim/full_system.hh"
#include "sim/redirect_path.hh"
-using namespace TheISA;
-
std::vector<System *> System::systemList;
void
@@ -128,7 +126,7 @@
# if THE_ISA != NULL_ISA
int port = getRemoteGDBPort();
if (port) {
- t.gdb = new RemoteGDB(sys, tc, port + id);
+ t.gdb = new TheISA::RemoteGDB(sys, tc, port + id);
t.gdb->listen();
}
# endif
@@ -378,18 +376,18 @@
Addr
System::allocPhysPages(int npages)
{
- Addr return_addr = pagePtr << PageShift;
+ Addr return_addr = pagePtr << TheISA::PageShift;
pagePtr += npages;
- Addr next_return_addr = pagePtr << PageShift;
+ Addr next_return_addr = pagePtr << TheISA::PageShift;
if (_m5opRange.contains(next_return_addr)) {
warn("Reached m5ops MMIO region\n");
return_addr = 0xffffffff;
- pagePtr = 0xffffffff >> PageShift;
+ pagePtr = 0xffffffff >> TheISA::PageShift;
}
- if ((pagePtr << PageShift) > physmem.totalSize())
+ if ((pagePtr << TheISA::PageShift) > physmem.totalSize())
fatal("Out of memory, please increase size of physical memory.");
return return_addr;
}
@@ -403,7 +401,7 @@
Addr
System::freeMemSize() const
{
- return physmem.totalSize() - (pagePtr << PageShift);
+ return physmem.totalSize() - (pagePtr << TheISA::PageShift);
}
bool
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39655
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966
Gerrit-Change-Number: 39655
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
