Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40176 )
Change subject: arch: Template the generic PC types on the instruction
width.
......................................................................
arch: Template the generic PC types on the instruction width.
These had been templated on a type, and then the width of that type was
considered the amount the PC should advance when executing straight line
code. That type was MachInst, which was loosely the size of an
instruction, but was practically whatever sized data type was fed into
the decoder at a time.
Instead of tying this to a type, this change moves it over to be a
simple number. This avoids a level of indirection, and also further
decouples the type the decoder might use as input from the instruction
size.
Change-Id: I797876a33d27e759c7a6e23a658179201fabfa47
---
M src/arch/arm/types.hh
M src/arch/generic/types.hh
M src/arch/mips/types.hh
M src/arch/power/types.hh
M src/arch/riscv/types.hh
M src/arch/sparc/types.hh
M src/arch/x86/types.hh
7 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index fa877be..c6ecdbd 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -211,11 +211,11 @@
Bitfield<11, 8> ltcoproc;
EndBitUnion(ExtMachInst)
- class PCState : public GenericISA::UPCState<MachInst>
+ class PCState : public GenericISA::UPCState<4>
{
protected:
- typedef GenericISA::UPCState<MachInst> Base;
+ typedef GenericISA::UPCState<4> Base;
enum FlagBits {
ThumbBit = (1 << 0),
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 76df835..fa192e2 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -147,7 +147,7 @@
*/
// The most basic type of PC.
-template <class MachInst>
+template <int InstWidth>
class SimplePCState : public PCStateBase
{
protected:
@@ -165,7 +165,7 @@
set(Addr val)
{
pc(val);
- npc(val + sizeof(MachInst));
+ npc(val + InstWidth;
};
void
@@ -180,7 +180,7 @@
bool
branching() const
{
- return this->npc() != this->pc() + sizeof(MachInst);
+ return this->npc() != this->pc() + InstWidth;
}
// Advance the PC.
@@ -188,24 +188,24 @@
advance()
{
_pc = _npc;
- _npc += sizeof(MachInst);
+ _npc += InstWidth;
}
};
-template <class MachInst>
+template <int InstWidth>
std::ostream &
-operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
+operator<<(std::ostream & os, const SimplePCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
return os;
}
// A PC and microcode PC.
-template <class MachInst>
-class UPCState : public SimplePCState<MachInst>
+template <int InstWidth>
+class UPCState : public SimplePCState<InstWidth>
{
protected:
- typedef SimplePCState<MachInst> Base;
+ typedef SimplePCState<InstWidth> Base;
MicroPC _upc;
MicroPC _nupc;
@@ -238,7 +238,7 @@
bool
branching() const
{
- return this->npc() != this->pc() + sizeof(MachInst) ||
+ return this->npc() != this->pc() + InstWidth ||
this->nupc() != this->upc() + 1;
}
@@ -268,7 +268,7 @@
}
bool
- operator == (const UPCState<MachInst> &opc) const
+ operator == (const UPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -276,7 +276,7 @@
}
bool
- operator != (const UPCState<MachInst> &opc) const
+ operator != (const UPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -298,9 +298,9 @@
}
};
-template <class MachInst>
+template <int InstWidth>
std::ostream &
-operator<<(std::ostream & os, const UPCState<MachInst> &pc)
+operator<<(std::ostream & os, const UPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x).(%d=>%d)",
pc.pc(), pc.npc(), pc.upc(), pc.nupc());
@@ -308,11 +308,11 @@
}
// A PC with a delay slot.
-template <class MachInst>
-class DelaySlotPCState : public SimplePCState<MachInst>
+template <int InstWidth>
+class DelaySlotPCState : public SimplePCState<InstWidth>
{
protected:
- typedef SimplePCState<MachInst> Base;
+ typedef SimplePCState<InstWidth> Base;
Addr _nnpc;
@@ -325,7 +325,7 @@
set(Addr val)
{
Base::set(val);
- nnpc(val + 2 * sizeof(MachInst));
+ nnpc(val + 2 * InstWidth);
}
DelaySlotPCState() {}
@@ -334,9 +334,9 @@
bool
branching() const
{
- return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
- (this->npc() == this->pc() + sizeof(MachInst) ||
- this->npc() == this->pc() + 2 * sizeof(MachInst)));
+ return !(this->nnpc() == this->npc() + InstWidth &&
+ (this->npc() == this->pc() + InstWidth ||
+ this->npc() == this->pc() + 2 * InstWidth));
}
// Advance the PC.
@@ -345,11 +345,11 @@
{
Base::_pc = Base::_npc;
Base::_npc = _nnpc;
- _nnpc += sizeof(MachInst);
+ _nnpc += InstWidth;
}
bool
- operator == (const DelaySlotPCState<MachInst> &opc) const
+ operator == (const DelaySlotPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -357,7 +357,7 @@
}
bool
- operator != (const DelaySlotPCState<MachInst> &opc) const
+ operator != (const DelaySlotPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -377,9 +377,9 @@
}
};
-template <class MachInst>
+template <int InstWidth>
std::ostream &
-operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
+operator<<(std::ostream & os, const DelaySlotPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x=>%#x)",
pc.pc(), pc.npc(), pc.nnpc());
@@ -387,11 +387,11 @@
}
// A PC with a delay slot and a microcode PC.
-template <class MachInst>
-class DelaySlotUPCState : public DelaySlotPCState<MachInst>
+template <int InstWidth>
+class DelaySlotUPCState : public DelaySlotPCState<InstWidth>
{
protected:
- typedef DelaySlotPCState<MachInst> Base;
+ typedef DelaySlotPCState<InstWidth> Base;
MicroPC _upc;
MicroPC _nupc;
@@ -445,7 +445,7 @@
}
bool
- operator == (const DelaySlotUPCState<MachInst> &opc) const
+ operator == (const DelaySlotUPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
@@ -454,7 +454,7 @@
}
bool
- operator != (const DelaySlotUPCState<MachInst> &opc) const
+ operator != (const DelaySlotUPCState<InstWidth> &opc) const
{
return !(*this == opc);
}
@@ -476,9 +476,9 @@
}
};
-template <class MachInst>
+template <int InstWidth>
std::ostream &
-operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
+operator<<(std::ostream & os, const DelaySlotUPCState<InstWidth> &pc)
{
ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index d7dd725..e287bd3 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -38,7 +38,7 @@
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-typedef GenericISA::DelaySlotPCState<MachInst> PCState;
+typedef GenericISA::DelaySlotPCState<4> PCState;
//used in FP convert & round function
enum ConvertType{
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index e37659c..1f4db94 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -76,7 +76,7 @@
Bitfield<19, 12> fxm;
EndBitUnion(ExtMachInst)
-typedef GenericISA::SimplePCState<MachInst> PCState;
+typedef GenericISA::SimplePCState<4> PCState;
// typedef uint64_t LargestRead;
// // Need to use 64 bits to make sure that read requests get handled
properly
diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh
index 38923b8..68c3f98 100644
--- a/src/arch/riscv/types.hh
+++ b/src/arch/riscv/types.hh
@@ -50,7 +50,7 @@
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-class PCState : public GenericISA::UPCState<MachInst>
+class PCState : public GenericISA::UPCState<4>
{
private:
bool _compressed;
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 885bdc9..ffb9806 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -38,7 +38,7 @@
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
+typedef GenericISA::DelaySlotUPCState<4> PCState;
}
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 9b0b034..7b7f824 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -283,10 +283,10 @@
return true;
}
-class PCState : public GenericISA::UPCState<MachInst>
+class PCState : public GenericISA::UPCState<8>
{
protected:
- typedef GenericISA::UPCState<MachInst> Base;
+ typedef GenericISA::UPCState<8> Base;
uint8_t _size;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I797876a33d27e759c7a6e23a658179201fabfa47
Gerrit-Change-Number: 40176
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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