Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40278 )
Change subject: fastmodel: add interface to update system counter freq
......................................................................
fastmodel: add interface to update system counter freq
This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.
Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40278
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.hh
10 files changed, 55 insertions(+), 4 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 1decdf9..11e8c98 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -41,6 +41,8 @@
{
for (auto *tc : threadContexts)
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
params().cntfrq);
+
+ evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
}
void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 29d8877..02ccaab 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -46,6 +46,13 @@
template <class Types>
void
+ScxEvsCortexA76<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+ periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
+template <class Types>
+void
ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
{
gem5CpuCluster = dynamic_cast<CortexA76Cluster *>(cluster);
@@ -86,6 +93,7 @@
}
clockRateControl.bind(this->clock_rate_s);
+ periphClockRateControl.bind(this->periph_clock_rate_s);
}
template <class Types>
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index fa12ff8..4aa43b6 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@
SC_HAS_PROCESS(ScxEvsCortexA76);
ClockRateControlInitiatorSocket clockRateControl;
+ ClockRateControlInitiatorSocket periphClockRateControl;
typedef sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@
void setClkPeriod(Tick clk_period) override;
+ void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
void setCluster(SimObject *cluster) override;
};
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931..04dae41 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[1];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a93..0279140 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[2];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index 9ce9027..b18b102 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[3];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
index e4b79ce..c7f1cb2 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[4];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index cd84aa6..f4ce61e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -45,6 +45,13 @@
template <class Types>
void
+ScxEvsCortexR52<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+ panic("Not implemented for R52.");
+}
+
+template <class Types>
+void
ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)
{
gem5CpuCluster = dynamic_cast<CortexR52Cluster *>(cluster);
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index e03a322..3fa5980 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -140,6 +140,8 @@
void setClkPeriod(Tick clk_period) override;
+ void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
void setCluster(SimObject *cluster) override;
};
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh
b/src/arch/arm/fastmodel/iris/cpu.hh
index c5dd19f..369f0d8 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -44,6 +44,7 @@
public:
virtual void sendFunc(PacketPtr pkt) = 0;
virtual void setClkPeriod(Tick clk_period) = 0;
+ virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Gerrit-Change-Number: 40278
Gerrit-PatchSet: 6
Gerrit-Owner: Earl Ou <[email protected]>
Gerrit-Reviewer: Earl Ou <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Yu-hsin Wang <[email protected]>
Gerrit-MessageType: merged
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