Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40098 )
Change subject: arch-arm,cpu: Introduce a getEMI virtual method on
StaticInst.
......................................................................
arch-arm,cpu: Introduce a getEMI virtual method on StaticInst.
This takes the place of direct access to the machInst field as used in
the MinorCPU model which makes the incorrect assumption that it can
arbitrarily treat the ExtMachInst as an integer, and that masking in a
certain way can meaningfully classify what the instruction will do.
Because that assumption is not correct in general, that had been
ifdef-ed out in most ISAs except ARM, and for the other ISAs the value
was simply set to zero.
Change-Id: I8ac05e65475edc3ccc044afdff09490e2c05ba07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40098
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/insts/static_inst.hh
M src/cpu/minor/func_unit.cc
M src/cpu/static_inst.hh
3 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index e101d93..908641c 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -197,6 +197,8 @@
pcState.advance();
}
+ uint64_t getEMI() const override { return machInst; }
+
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 58f3a1e..8c5e3a6 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -171,13 +171,12 @@
MinorFUTiming *
FUPipeline::findTiming(const StaticInstPtr &inst)
{
-#if THE_ISA == ARM_ISA
- /* This should work for any ISA with a POD mach_inst */
- TheISA::ExtMachInst mach_inst = inst->machInst;
-#else
- /* Just allow extra decode based on op classes */
- uint64_t mach_inst = 0;
-#endif
+ /*
+ * This will only work on ISAs with an instruction format with a fixed
size
+ * which can be categorized using bit masks. This is really only
supported
+ * on ARM and is a bit of a hack.
+ */
+ uint64_t mach_inst = inst->getEMI();
const std::vector<MinorFUTiming *> &timings =
description.timings;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 09f171f..b2cd508 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -258,6 +258,8 @@
/// The binary machine instruction.
const TheISA::ExtMachInst machInst;
+ virtual uint64_t getEMI() const { return 0; }
+
protected:
/**
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8ac05e65475edc3ccc044afdff09490e2c05ba07
Gerrit-Change-Number: 40098
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Daniel Carvalho <[email protected]>
Gerrit-MessageType: merged
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