Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40597 )
Change subject: arch-riscv: Implementation of CLINT
......................................................................
arch-riscv: Implementation of CLINT
This patch implements the CLINT device model based
on the SiFive U54MC datasheet. Currently, the RTC
is included in the CLINT device model. This will be
moved out in future patches. Instead, CLINT will receive
the clock signal via an InterruptPin.
isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).
Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
---
M src/arch/riscv/isa.cc
A src/dev/riscv/Clint.py
A src/dev/riscv/SConscript
A src/dev/riscv/clint.cc
A src/dev/riscv/clint.hh
5 files changed, 484 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 8401310..2251f9f 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -261,7 +261,7 @@
if (hpmCounterEnabled(MISCREG_TIME)) {
DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
std::time(nullptr));
- return std::time(nullptr);
+ return readMiscRegNoEffect(MISCREG_TIME);
} else {
warn("Wall clock disabled.\n");
return 0;
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
new file mode 100644
index 0000000..8d527f7
--- /dev/null
+++ b/src/dev/riscv/Clint.py
@@ -0,0 +1,49 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+
+class Clint(BasicPioDevice):
+ type = 'Clint'
+ cxx_header = 'dev/riscv/clint.hh'
+ intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+ time = Param.Time('01/01/2009', "System time ('Now' for actual time)")
+ frequency = Param.Frequency("1MHz", "RTC Frequency")
+ pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
new file mode 100755
index 0000000..b2092ca
--- /dev/null
+++ b/src/dev/riscv/SConscript
@@ -0,0 +1,36 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+ SimObject('Clint.py')
+
+ DebugFlag('RiscvClint')
+
+ Source('clint.cc')
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
new file mode 100644
index 0000000..65503db
--- /dev/null
+++ b/src/dev/riscv/clint.cc
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dev/riscv/clint.hh"
+
+#include "debug/RiscvClint.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "params/Clint.hh"
+#include "sim/system.hh"
+
+using namespace RiscvISA;
+
+Clint::Clint(const Params ¶ms) :
+ BasicPioDevice(params, params.pio_size),
+ system(params.system),
+ intrctrl(params.intrctrl),
+ rtc(this, params.name + ".rtc", params.time,
+ false, params.frequency, this),
+ registers(params.name + ".registers", params.pio_addr, this)
+{
+}
+
+void
+Clint::RTC::handleEvent()
+{
+ clint->tickTimer();
+}
+
+void
+Clint::tickTimer()
+{
+ // Increment mtime
+ uint64_t& mtime = registers.mtime.get();
+ mtime++;
+
+ for (int context_id = 0; context_id < nThread; context_id++) {
+
+ // Update misc reg file
+ system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME,
mtime);
+
+ // Post timer interrupt
+ uint64_t mtimecmp = registers.mtimecmp[context_id].get();
+ if (mtime >= mtimecmp) {
+ if (mtime == mtimecmp) {
+ DPRINTF(RiscvClint,
+ "MTIP posted - thread: %d, mtime: %d,
mtimecmp: %d\n",
+ context_id, mtime, mtimecmp);
+ }
+ intrctrl->post(context_id, ExceptionCode::INT_TIMER_MACHINE,
0);
+ } else {
+ intrctrl->clear(context_id, ExceptionCode::INT_TIMER_MACHINE,
0);
+ }
+ }
+}
+
+void
+Clint::ClintRegisters::init()
+{
+ // Calculate reserved space size
+ const size_t reserved0_size = 0x4000 - clint->nThread * 4;
+ reserved.emplace_back("reserved0", reserved0_size);
+ const size_t reserved1_size = 0xBFF8 - 0x4000 - clint->nThread * 8;
+ reserved.emplace_back("reserved1", reserved1_size);
+
+ // Initialize registers
+ for (int i = 0; i < clint->nThread; i++) {
+ ThreadID id {i};
+ msip.emplace_back(std::string("msip") + std::to_string(i), id, 0);
+ mtimecmp.emplace_back(std::string("mtimecmp") + std::to_string(i),
0);
+ }
+
+ // Add registers to bank
+ for (int i = 0; i < clint->nThread; i++) {
+ msip[i].beforeRead(clint, &Clint::readMSIP);
+ msip[i].afterWrite(clint, &Clint::writeMSIP);
+ addRegister(msip[i]);
+ }
+ addRegister(reserved[0]);
+ for (int i = 0; i < clint->nThread; i++) {
+ addRegister(mtimecmp[i]);
+ }
+ addRegister(reserved[1]);
+ mtime.readonly();
+ addRegister(mtime);
+}
+
+void
+Clint::readMSIP(MSIPRegister& reg)
+{
+ auto tc = system->threads[reg.getProp().thread_id];
+ RegVal mip = tc->readMiscReg(MISCREG_IP);
+ uint32_t msip = bits<uint32_t>(mip,
ExceptionCode::INT_SOFTWARE_MACHINE);
+ reg.update(msip);
+};
+
+void
+Clint::writeMSIP(MSIPRegister& reg)
+{
+ uint32_t msip = reg.get();
+ int thread_id = reg.getProp().thread_id;
+ assert(msip <= 1);
+ if (msip > 0) {
+ DPRINTF(RiscvClint,
+ "MSIP posted - thread: %d\n", thread_id);
+ intrctrl->post(thread_id,
+ ExceptionCode::INT_SOFTWARE_MACHINE, 0);
+ } else {
+ DPRINTF(RiscvClint,
+ "MSIP cleared - thread: %d\n", thread_id);
+ intrctrl->clear(thread_id,
+ ExceptionCode::INT_SOFTWARE_MACHINE, 0);
+ }
+};
+
+Tick
+Clint::read(PacketPtr pkt)
+{
+ // Check for atomic operation
+ bool is_atomic = pkt->isAtomicOp() && pkt->cmd == MemCmd::SwapReq;
+ DPRINTF(RiscvClint,
+ "Read request - addr: %#x, size: %#x, atomic:%d\n",
+ pkt->getAddr(), pkt->getSize(), is_atomic);
+
+ // Perform register read
+ registers.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
+
+ if (is_atomic) {
+ // Perform atomic operation
+ (*(pkt->getAtomicOp()))(pkt->getPtr<uint8_t>());
+ return write(pkt);
+ } else {
+ pkt->makeResponse();
+ return pioDelay;
+ }
+}
+
+Tick
+Clint::write(PacketPtr pkt)
+{
+ DPRINTF(RiscvClint,
+ "Write request - addr: %#x, size: %#x\n",
+ pkt->getAddr(), pkt->getSize());
+
+ // Perform register write
+ registers.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
+
+ pkt->makeResponse();
+ return pioDelay;
+}
+
+void
+Clint::startup()
+{
+ rtc.startup();
+}
+
+void
+Clint::init()
+{
+ nThread = system->threads.size();
+ registers.init();
+ BasicPioDevice::init();
+}
+
+void
+Clint::serialize(CheckpointOut &cp) const
+{
+ for (auto const ®: registers.msip) {
+ paramOut(cp, reg.name(), reg);
+ }
+ for (auto const ®: registers.mtimecmp) {
+ paramOut(cp, reg.name(), reg);
+ }
+ paramOut(cp, "mtime", registers.mtime);
+}
+
+void
+Clint::unserialize(CheckpointIn &cp)
+{
+ for (auto ®: registers.msip) {
+ paramIn(cp, reg.name(), reg);
+ }
+ for (auto ®: registers.mtimecmp) {
+ paramIn(cp, reg.name(), reg);
+ }
+ paramIn(cp, "mtime", registers.mtime);
+}
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
new file mode 100644
index 0000000..cf12f70
--- /dev/null
+++ b/src/dev/riscv/clint.hh
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_RISCV_CLINT_HH__
+#define __DEV_RISCV_CLINT_HH__
+
+#include "arch/riscv/interrupts.hh"
+#include "arch/riscv/registers.hh"
+#include "cpu/intr_control.hh"
+#include "dev/io_device.hh"
+#include "dev/mc146818.hh"
+#include "dev/reg_bank.hh"
+#include "dev/riscv/reg_bank.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "params/Clint.hh"
+#include "sim/system.hh"
+
+using namespace RiscvISA;
+
+/**
+ * NOTE:
+ * This implementation of CLINT is based on
+ * the SiFive U54MC datasheet.
+ */
+
+/**
+ * TODO:
+ * - Enforce access control
+ * - Separate RTC as MMIO device
+ * - Use InterruptPin to receive mtime increment signal
+ */
+class Clint : public BasicPioDevice
+{
+ // Params
+ protected:
+ System *system;
+ IntrControl *intrctrl;
+ int nThread;
+
+ public:
+ typedef ClintParams Params;
+
+ const Params &
+ params() const
+ {
+ return dynamic_cast<const Params &>(_params);
+ }
+ Clint(const Params ¶ms);
+
+ // RTC
+ public:
+ /**
+ * RTC Clock Model
+ * Can be separated out as a PioDevice to provide wall clock time.
+ */
+ class RTC: public MC146818
+ {
+ public:
+ Clint *clint;
+
+ RTC(EventManager *em, const std::string &n,
+ const struct tm time, bool bcd, Tick frequency, Clint *clint):
+ MC146818(em, n, time, bcd, frequency), clint(clint) {}
+
+ protected:
+ /**
+ * RTC interrupt callback. Increments mtime.
+ * Used to control effective RTC frequency.
+ */
+ void handleEvent();
+ } rtc;
+
+ /**
+ * Timer tick callback. Separated from RTC class
+ * for easier implementation of a separate RTC
+ * PioDevice.
+ */
+ void tickTimer();
+
+ // Register bank
+ public:
+
+ /**
+ * MMIO Registers
+ * 0x0000 - 0x3FFF: msip (write-through to misc reg file)
+ * ...: reserved[0]
+ * 0x4000 - 0xBFF7: mtimecmp
+ * ...: reserved[1]
+ * 0xBFF8: mtime (read-only)
+ */
+ class ClintRegisters: public PropRegisterBankLE {
+
+ public:
+ struct ThreadID {
+ int thread_id;
+ };
+
+ using MSIPRegister = PropRegister<ThreadID, uint32_t>;
+
+ std::vector<MSIPRegister> msip;
+ std::vector<Register64> mtimecmp;
+ Register64 mtime = {"mtime", 0};
+ std::vector<RegisterRaz> reserved;
+
+ ClintRegisters(const std::string &name, Addr base, Clint* clint) :
+ PropRegisterBankLE(name, base),
+ clint(clint) {}
+
+ Clint *clint;
+
+ void init();
+
+ } registers;
+
+ /**
+ * Register read / write callbacks
+ */
+ using MSIPRegister = ClintRegisters::MSIPRegister;
+ void readMSIP(MSIPRegister& reg);
+ void writeMSIP(MSIPRegister& reg);
+
+ // External API
+ public:
+ /**
+ * PioDevice interface functions
+ */
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
+
+ /**
+ * SimObject functions
+ */
+ void startup() override;
+ void init() override;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+};
+
+
+#endif // __DEV_RISCV_CLINT_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
Gerrit-Change-Number: 40597
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <[email protected]>
Gerrit-MessageType: newchange
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