Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40880 )
Change subject: arch-power: Remove pre-execute zero register update
......................................................................
arch-power: Remove pre-execute zero register update
The Power architecture does not define a zero register but
the simulator expects one and always sets it to zero in the
pre-execute stage of an instruction. This update shows up
in the logs when running the simulator with debug flags and
can be confusing as no instructions actually modify it.
This removes the redundant updates for this architecture.
Change-Id: I5e449f0144fcf4fbcaa15aed8166f132aa17bb10
Signed-off-by: Sandipan Das <[email protected]>
---
M src/cpu/simple/base.cc
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0941388..cecd9ac 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -307,8 +307,10 @@
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
+#if THE_ISA != POWER_ISA
// maintain $r0 semantics
thread->setIntReg(TheISA::ZeroReg, 0);
+#endif
// resets predicates
t_info.setPredicate(true);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e449f0144fcf4fbcaa15aed8166f132aa17bb10
Gerrit-Change-Number: 40880
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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