Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40894 )
Change subject: arch-power: Fix disassembly for load-store instructions
......................................................................
arch-power: Fix disassembly for load-store instructions
This fixes disassembly generated for load-store instructions
based on how the base classess that are used to distinguish
between the types of operands used by these instructions.
Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
2 files changed, 158 insertions(+), 5 deletions(-)
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 596d78d..94508a7 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -38,6 +38,7 @@
return csprintf("%-10s", mnemonic);
}
+
std::string
MemDispOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
@@ -59,16 +60,162 @@
// Print the data register for a store
else {
- printReg(ss, srcRegIdx(1));
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
}
// Print the displacement
- ss << ", " << (int32_t)disp;
-
- // Print the address register
+ ss << ", " << disp;
ss << "(";
- printReg(ss, srcRegIdx(0));
+
+ // Print the address register for a load
+ if (!flags[IsStore]) {
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // The address register is skipped if it is R0
+ else {
+ ss << "0";
+ }
+ }
+
+ // Print the address register for a store
+ else {
+ if (_numSrcRegs > 1) {
+ printReg(ss, srcRegIdx(1));
+ }
+
+ // The address register is skipped if it is R0
+ else {
+ ss << "0";
+ }
+ }
+
ss << ")";
return ss.str();
}
+
+
+std::string
+MemDispShiftOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // Print the destination only for a load
+ if (!flags[IsStore]) {
+ if (_numDestRegs > 0) {
+
+ // If the instruction updates the source register with the
+ // EA, then this source register is placed in position 0,
+ // therefore we print the last destination register.
+ printReg(ss, destRegIdx(_numDestRegs-1));
+ }
+ }
+
+ // Print the data register for a store
+ else {
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
+ }
+
+ // Print the displacement
+ ss << ", " << (disp << 2);
+ ss << "(";
+
+ // Print the address register for a load
+ if (!flags[IsStore]) {
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // The address register is skipped if it is R0
+ else {
+ ss << "0";
+ }
+ }
+
+ // Print the address register for a store
+ else {
+ if (_numSrcRegs > 1) {
+ printReg(ss, srcRegIdx(1));
+ }
+
+ // The address register is skipped if it is R0
+ else {
+ ss << "0";
+ }
+ }
+
+ ss << ")";
+
+ return ss.str();
+}
+
+
+std::string
+MemIndexOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // Print the destination only for a load
+ if (!flags[IsStore]) {
+ if (_numDestRegs > 0) {
+
+ // If the instruction updates the source register with the
+ // EA, then this source register is placed in position 0,
+ // therefore we print the last destination register.
+ printReg(ss, destRegIdx(_numDestRegs-1));
+ }
+ }
+
+ // Print the data register for a store
+ else {
+ if (_numSrcRegs > 0) {
+ printReg(ss, srcRegIdx(0));
+ }
+ }
+
+ ss << ", ";
+
+ // Print the address registers for a load
+ if (!flags[IsStore]) {
+ if (_numSrcRegs > 1) {
+ printReg(ss, srcRegIdx(0));
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+
+ // The first address register is skipped if it is R0
+ else if (_numSrcRegs > 0) {
+ ss << "0, ";
+ printReg(ss, srcRegIdx(0));
+ }
+ }
+
+ // Print the address registers for a store
+ else {
+ if (_numSrcRegs > 2) {
+ printReg(ss, srcRegIdx(1));
+ ss << ", ";
+ printReg(ss, srcRegIdx(2));
+ }
+
+ // The first address register is skipped if it is R0
+ else if (_numSrcRegs > 1) {
+ ss << "0, ";
+ printReg(ss, srcRegIdx(1));
+ }
+ }
+
+ return ss.str();
+}
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index d14f1e6..f800ae3 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -90,6 +90,9 @@
disp(sext<14>(machInst.ds))
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
@@ -105,6 +108,9 @@
: MemOp(mnem, _machInst, __opClass)
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Gerrit-Change-Number: 40894
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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